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SST39VF016-55-4C-B2K Datasheet

  • SST39VF016-55-4C-B2K

  • x8 Flash EEPROM

  • 251.01KB

  • 24頁

  • ETC

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8 Mbit / 16 Mbit (x8) Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
FEATURES:
鈥?Organized as 1M x8 / 2M x8
鈥?Single Voltage Read and Write Operations
- 3.0-3.6V for SST39LF080/016
- 2.7-3.6V for SST39VF080/016
鈥?Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
鈥?Low Power Consumption:
- Active Current: 15 mA (typical)
- Standby Current: 4 碌A(chǔ) (typical)
- Auto Low Power Mode: 4 碌A(chǔ) (typical)
鈥?Sector-Erase Capability
- Uniform 4 KByte sectors
鈥?Block-Erase Capability
- Uniform 64 KByte blocks
鈥?Fast Read Access Time:
- 55 ns for SST39LF080/016
- 70 and 90 ns for SST39VF080/016
鈥?Latched Address and Data
PRODUCT DESCRIPTION
The SST39LF/VF080 and SST39LF/VF016 devices are
1M x8 / 2M x8 CMOS Multi-Purpose Flash (MPF)
manufactured with SST鈥檚 proprietary, high performance
CMOS SuperFlash technology. The split-gate cell de-
sign and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST39LF080/016 write (Program or
Erase) with a 3.0-3.6V power supply. The
SST39VF080/016 write (Program or Erase) with a 2.7-
3.6V power supply. They conform to JEDEC standard
pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39LF/VF080 and SST39LF/VF016 devices provide
a typical Byte-Program time of 14 碌sec. The devices use
Toggle Bit or Data# Polling to indicate the completion of
Program operation. To protect against inadvertent write,
they have on-chip hardware and Software Data Protec-
tion schemes. Designed, manufactured, and tested for
a wide spectrum of applications, these devices are
offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST39LF/VF080 and SST39LF/VF016 devices are
suited for applications that require convenient and eco-
nomical updating of program, configuration, or data
memory. For all system applications, they significantly
improve performance and reliability, while lowering power
consumption. They inherently use less energy during
鈥?Fast Erase and Byte-Program:
- Sector-Erase Time: 18 ms (typical)
- Block-Erase Time: 18 ms (typical)
- Chip-Erase Time: 70 ms (typical)
- Byte-Program Time: 14 碌s (typical)
- Chip Rewrite Time:
15 seconds (typical) for SST39LF/VF080
30 seconds (typical) for SST39LF/VF016
鈥?Automatic Write Timing
- Internal V
PP
Generation
鈥?End-of-Write Detection
- Toggle Bit
- Data# Polling
鈥?CMOS I/O Compatibility
鈥?JEDEC Standard
-
Flash EEPROM Pinouts and command sets
鈥?Packages Available
- 40-Pin TSOP (10mm x 20mm)
- 48-Ball TFBGA (6mm x 8mm)
Erase and Program than alternative flash technologies.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. They also
improve flexibility while lowering the cost for program, data,
and configuration storage applications.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose Erase and Program times increase
with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39LF/VF080 and SST39LF/VF016 are offered in
40-pin TSOP and 48-ball TFBGA packaging. See
Figures 1 and 2 for pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write se-
quences. A command is written by asserting WE# low
while keeping CE# low. The address bus is latched on
the falling edge of WE# or CE#, whichever occurs last.
The data bus is latched on the rising edge of WE# or
CE#, whichever occurs first.
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漏 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
396-2 11/00
S71146
These specifications are subject to change without notice.
1

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