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SST34HF3243B-90-4E-LP Datasheet

  • SST34HF3243B-90-4E-LP

  • MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC

  • 362.24KB

  • 30頁(yè)

  • ETC

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32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF3223B / SST34HF3243B
SST34HF3223B / SST24HF3243B32 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemories
Preliminary Information
FEATURES:
鈥?Flash Organization: Two 1M x16
鈥?Quad-Bank Architecture for Concurrent
Read-While-Write Operation
鈥?12 Mbit + 4 Mbit + 12 Mbit + 4 Mbit
鈥?SRAM Organization:
鈥?2 Mbit: 256K x8 or 128K x16
鈥?4 Mbit: 512K x8 or 256K x16
鈥?Single 2.7-3.3V Read-While-Write Operations
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Low Power Consumption:
鈥?Active Current: 35 mA (typical)
鈥?Standby Current: 25 碌A(chǔ) (typical)
鈥?Sector-Erase Capability
鈥?Uniform 1 KWord sectors
鈥?Block-Erase Capability
鈥?Uniform 32 KWord blocks
鈥?Read Access Time
鈥?Flash: 70 and 90 ns
鈥?SRAM: 70 and 90 ns
鈥?Latched Address and Data
鈥?Fast Erase and Word-Program:
鈥?Sector-Erase Time: 18 ms (typical)
鈥?Block-Erase Time: 18 ms (typical)
鈥?Chip-Erase Time: 70 ms (typical)
鈥?Word-Program Time: 14 碌s (typical)
鈥?Chip Rewrite Time: 30 seconds (typical)
鈥?Automatic Write Timing
鈥?Internal V
PP
Generation
鈥?End-of-Write Detection
鈥?Toggle Bit
鈥?Data# Polling
鈥?CMOS I/O Compatibility
鈥?JEDEC Standard Command Set
鈥?Packages Available
鈥?56-ball LFBGA (10mm x 12mm x 1.4mm)
PRODUCT DESCRIPTION
The SST34HF3223B/3243B ComboMemory devices inte-
grate four CMOS flash memory banks with a 256K x8 /
128K x16 or 512K x8 / 256K x16 CMOS SRAM memory
bank in a Multi-Chip Package (MCP). These devices are
fabricated using SST鈥檚 proprietary, high-performance
CMOS SuperFlash technology incorporating the split-gate
cell design and thick oxide tunneling injector to attain better
reliability and manufacturability compared with alternate
approaches. The SST34HF3223B/3243B devices are
ideal for applications such as cellular phones, PDAs and
other portable electronic devices in a low power and small
form factor system.
The SST34HF3223B/3243B features multiple flash mem-
ory bank architecture allowing for concurrent operations
between the four flash memory banks and the SRAM. The
devices can read data from either bank while an Erase or
Program operation is in progress in the opposite bank. The
four flash memory banks are partitioned as two 12 Mbit
and two 4 Mbit for storing boot code, program code, config-
uration/parameter data and user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
漏2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
543
1
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF3223B/3243B devices offer a
typical endurance of 100,000 cycles. Data retention is rated
at greater than 100 years. With high performance Word-
Program, the flash memory banks provide a typical Word-
Program time of 14 碌sec. The entire flash memory bank
can be erased and programmed word-by-word in typically
30 seconds for the SST34HF3223B/3243B, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent flash write, the SST34HF3223B/3243B
devices contain on-chip hardware and software data pro-
tection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signal, BES1# and BES2, selects the
SRAM bank. The flash memory bank enable signal, BEF#
(BEF1# or BEF2#), has to be used with Software Data Pro-
tection (SDP) command sequence when controlling the
Erase and Program operations in the flash memory bank.
The memory banks are superimposed in the same mem-
ory address space where they share common address
lines, data lines, WE# and OE# which minimize power con-
sumption and area.
The SST logo and SuperFlash are Trademarks registered by Silicon Storage Technology, Inc. in the U.S. Patent and Trademark Office.
Concurrent SuperFlash, CSF, and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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