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SST29VE010-120-3C-PH Datasheet

  • SST29VE010-120-3C-PH

  • 1 Megabit (128K x 8) Page Mode EEPROM

  • 27頁(yè)

  • SST   SST

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1 Megabit (128K x 8) Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Data Sheet
FEATURES:
鈥?Single Voltage Read and Write Operations
鈥?5.0V-only for the 29EE010
鈥?3.0V-only for the 29LE010
鈥?2.7V-only for the 29VE010
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Low Power Consumption
鈥?Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
鈥?Standby Current: 10 碌A(chǔ) (typical)
鈥?Fast Page-Write Operation
鈥?128 Bytes per Page, 1024 Pages
鈥?Page-Write Cycle: 5 ms (typical)
鈥?Complete Memory Rewrite: 5 sec (typical)
鈥?Effective Byte-write Cycle Time: 39 碌s
(typical)
鈥?Fast Read Access Time
鈥?5.0V-only operation: 90 and 120 ns
鈥?3.0V-only operation: 150 and 200 ns
鈥?2.7V-only operation: 200 and 250 ns
鈥?Latched Address and Data
鈥?Automatic Write Timing
鈥?Internal V
pp
Generation
鈥?End of Write Detection
鈥?Toggle Bit
鈥?Data# Polling
鈥?Hardware and Software Data Protection
鈥?TTL I/O Compatibility
鈥?JEDEC Standard Byte-wide EEPROM Pinouts
鈥?Packages Available
鈥?32-Pin TSOP (8x20 & 8x14 mm)
鈥?32-Lead PLCC
鈥?32 Pin Plastic DIP
1
2
3
4
5
6
7
PRODUCT DESCRIPTION
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS
page mode EEPROMs manufactured with SST鈥檚 propri-
etary, high performance CMOS SuperFlash technology.
The split gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches. The 29EE010/
29LE010/29VE010 write with a single power supply.
Internal Erase/Program is transparent to the user. The
29EE010/29LE010/29VE010 conform to JEDEC stan-
dard pinouts for byte-wide memories.
Featuring high performance page write, the 29EE010/
29LE010/29VE010 provide a typical byte-write time of
39 碌sec. The entire memory, i.e., 128K bytes, can be
written page by page in as little as 5 seconds, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of a write cycle. To protect
against inadvertent write, the 29EE010/29LE010/
29VE010 have on-chip hardware and software data
protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, the 29EE010/
29LE010/29VE010 are offered with a guaranteed page-
write endurance of 10
4
or 10
3
cycles. Data retention is
rated at greater than 100 years.
The 29EE010/29LE010/29VE010 are suited for applica-
tions that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, the 29EE010/29LE010/29VE010 signifi-
cantly improve performance and reliability, while lower-
ing power consumption, when compared with floppy disk
or EPROM approaches. The 29EE010/29LE010/
29VE010 improve flexibility while lowering the cost for
program, data, and configuration storage applications.
To meet high density, surface mount requirements, the
29EE010/29LE010/29VE010 are offered in 32-pin
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
PDIP package is also available. See Figures 1 and 2 for
pinouts.
Device Operation
The SST page mode EEPROM offers in-circuit electrical
write capability. The 29EE010/29LE010/29VE010 does
not require separate erase and program operations. The
internally timed write cycle executes both erase and
program transparently to the user. The 29EE010/
29LE010/29VE010 have industry standard optional
Software Data Protection, which SST recommends al-
ways to be enabled. The 29EE010/29LE010/29VE010
are compatible with industry standard EEPROM pinouts
and functionality.
Read
The Read operations of the 29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
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漏 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
304-04 12/97
1

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