SPT7750BIK Datasheet

IC型號：
SPT7750BIK
PDF描述：
8-BIT, 500 MSPS, FLASH A/D CONVERTER
文件大?。?/label>
89.95KB
PDF頁數(shù)：
8頁
芯片廠家：
FAIRCHILD

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SPT7750

8-BIT, 500 MSPS, FLASH A/D CONVERTER

TECHNICAL DATA

FEATURES

鈥?/div>

1:2 Demuxed ECL compatible outputs

Wide input bandwidth 鈥?900 MHz

Low input capacitance 鈥?15 pF

Metastable errors reduced to 1 LSB

Monolithic for low cost

Gray code output

APPLICATIONS

鈥?/div>

Digital oscilloscopes

Transient capture

Radar, EW, ECM

Direct RF down-conversion

NOVEMBER 30, 2001

GENERAL DESCRIPTION

The SPT7750 is a full parallel (flash) analog-to-digital con-

verter capable of digitizing full scale (0 to 鈥? V) inputs into

eight-bit digital words at an update rate of 500 MSPS. The

ECL-compatible outputs are demultiplexed into two sepa-

rate output banks, each with differential data ready out-

puts to ease the task of data capture. The SPT7750鈥檚 wide

input bandwidth and low capacitance eliminate the need

for external track-and-hold amplifiers for most applica-

tions. A proprietary decoding scheme reduces metastable

errors to the 1 LSB level. The SPT7750 operates from a

single 鈥?.2 V supply, with a nominal power dissipation of

5.5 W.

The SPT7750 is available in an 80-lead surface-mount

MQuad package over the industrial temperature range

(鈥?5 擄C to +85 擄C) and in die form.

BLOCK DIAGRAM

Analog

Input

Preamp

Comparator

256

CLK CLK

CLOCK

BUFFER

DEMUX

CLOCK

BUFFER

255

(OVR)

(MSB)

DRB (DATA READY)

D8B

D7B

D6B

D5B

D4B

D3B

D2B

DRB (DATA READY)

D8B (OVR)

D7B (MSB)

D5B

D6B

152

256 TO 8 Bit Decoder

With Metastable Error Correction

ECL Output Buffers And Latches

151

D4B

D3B

D2B

D1B

D0B (LSB)

DRA (DATA READY)

D8A (OVR)

D7A (MSB)

D5A

D4A

D3A

D2A

D1A

D0A (LSB)

D6A

1:2 DEMULTIPLEXER

128

D1B

D0B

127

D8A

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

(LSB)

BANK A

BANK B

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