SP8400
Very Low Phase Noise Synthesiser Divider
DS3739 - 2.1 April 1994
The SP8400 is a very low phase noise programmable
divider which is based on a divide by 8/9 dual modulus
prescaler and a 12 stage control counter. This gives a minimum
division ratio of 56 (64 for fractional - N synthesis applications),
and a maximum division ratio of 4103. Special circuit
techniques have been used to reduce the phase noise
considerably below that produced by standard dividers.The
data inputs are CMOS or TTL compatible.
The SP8400 is packaged in a 28 pin plastic SO package.
M2
M1
M0
V
CC
+5V
GND
CLOCK INPUT
CLOCK INPUT
CLOCK INPUT
CLOCK INPUT
GND
V
CC
+5V
V
CC
+5V
GND
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
M3
M4
M5
M6
M7
M8
N/C
OUTPUT
OUTPUT
N/C
V
CC
+5V
N/C
A2
A1
FEATURES
s
Very low Phase Noise (Typically -156dBc/Hz at 1kHz
offset)
s
Supply Voltage 5V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Output Current
Storage Temperature Range
Maximum Clock Input Voltage
6.5V
20mA
-55擄C to +125擄C
2.5V p-p
MP28
Fig.1 Pin connections - top view
ORDERING INFORMATION
SP8400 KG MPES(Commercial Grade)
0
鈥?0
鈥?0
鈥?0
鈥?0
鈥?0
(f) (dBc/Hz) 鈥?dB
鈥?0
鈥?0
鈥?0
鈥?0
鈥?00
鈥?10
鈥?20
鈥?30
鈥?40
鈥?50
鈥?60
鈥?70
10
100
1k
Frequency (Hz)
10k
100k
Fig.2 Typical single sideband phase noise measured at 300MHz
1
2
3
4
5
6
