錚?/div>
-compatible mode
鈥?Reverse Byte mode
鈥?Reverse Nibble mode
鈥?ECP (extended capabilities port) mode
with run-length encoding/decoding
鈥?EPP (enhanced parallel port) mode
鈥?Up to 2-Mbytes/sec. transfer rate in ECP
and EPP modes
s
64-byte parallel FIFO with DMA interface
鈥?64-byte FIFO can accommodate up to 4
Kbytes of compressed data with RLE
(run-length encoded) compression
enabled
s
s
Supports peripheral-side operation
Data and control input/output pads support
IEEE STD1284 level-2 interface
specification
CPU bus interface
鈥?High-speed slave DMA handshake
interface
鈥?Three clocks per word DMA transfers
鈥?On-the-fly data compression using RLE
(run-length encoded) encoding and
decoding
8/16-bit data interface
鈥?BYTESWAP input provides easy
interface to both Big- and Little-Endian
systems
鈥?Vectored interrupts simplify interrupt
service routines
System clock up to 25 MHz
CMOS technology enables high speed and
low power
Available in a 100-pin MQFP package
General
s
s
s
As of May 2001, this document replaces the Basis
Communications Corp. document
CL-CD1283 鈥?IEEE 1284-Compatible Parallel Interface.
May 2001