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SCAN921224SLC Datasheet

  • SCAN921224SLC

  • 20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer

  • 20頁

  • NSC

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SCAN921023/SCAN921224 20-66 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1
(JTAG) and at-speed BIST
April 2001
SCAN921023 and SCAN921224
20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
General Description
The SCAN921023 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921224 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock. Both devices are compliant with
IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TDI), Test Data Out (TDO), Test Mode
Select (TMS), Test Clock (TCK), and the optional Test Reset
(TRST). IEEE 1149.1 features provide the designer or test
engineer access to the backplane or cable interconnects and
the ability to verify differential signal integrity to enhance
their system test strategy. The pair of devices also features
an at-speed BIST mode which allows the interconnects be-
tween the Serializer and Deserializer to be verified at-speed.
The SCAN921023 transmits data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits clock and data bits serially, it eliminates clock-to-
data and data-to-data skew. The powerdown pin saves
power by reducing supply current when not using either
device. Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the Deserializer to
use the synchronization-to-random-data feature. By using
the synchronization mode, the Deserializer will establish lock
to a signal within specified lock times. In addition, the em-
bedded clock guarantees a transition on the bus every 12-bit
cycle. This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921023 output pins into TRI-STATE to achieve a high
impedance state. The PLL can lock to frequencies between
20 MHz and 66 MHz.
Features
n
IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n
Clock recovery from PLL lock to random data patterns.
n
Guaranteed transition every data transfer cycle
n
Chipset (Tx + Rx) power consumption
<
500 mW (typ)
@
66 MHz
n
Single differential pair eliminates multi-channel skew
n
Flow-through pinout for easy PCB layout
n
660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
n
10-bit parallel interface for 1 byte data plus 2 control bits
n
Synchronization mode and LOCK indicator
n
Programmable edge trigger on clock
n
High impedance on receiver inputs when power is off
n
Bus LVDS serial output rated for 27鈩?load
n
Small 49-lead BGA package
Block Diagrams
DS200001-1
漏 2001 National Semiconductor Corporation
DS200001
www.national.com

SCAN921224SLC 產(chǎn)品屬性

  • National Semiconductor (TI)

  • 10

  • 1

  • 660 Mbps

  • 3.3 V

  • + 85 C

  • FBGA

  • Tray

  • - 40 C

  • SMD/SMT

  • 416

  • 3.6 V

  • 3 V

  • LVCMOS, LVTTL

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