SCAN18373T Transparent Latch with 3-STATE Outputs
October 1991
Revised May 2000
SCAN18373T
Transparent Latch with 3-STATE Outputs
General Description
The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-
bit bytes with byte-oriented latch enable and output enable
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architec-
ture with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
s
IEEE 1149.1 (JTAG) Compliant
s
Buffered active-low latch enable
s
3-STATE outputs for bus-oriented applications
s
9-bit data busses for parity applications
s
Reduced-swing outputs source 32 mA/sink 64 mA
s
Guaranteed to drive 50
鈩?/div>
transmission line to TTL input
levels of 0.8V and 2.0V
s
TTL compatible inputs
s
25 mil pitch SSOP (Shrink Small Outline Package)
s
Includes CLAMP and HIGHZ instructions
s
Member of Fairchild鈥檚 SCAN Products
Ordering Code:
Order Number
SCAN1837TSSC
Package Number
MS56A
Package Description
Device also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
AI
(0鈥?)
, BI
(0鈥?)
ALE, BLE
AOE
1
, BOE
1
AO
(0鈥?)
, BO
(0鈥?)
Data Inputs
Latch Enable Inputs
3-STATE Output Enable Inputs
3-STATE Latch Outputs
Description
Truth Tables
Inputs
ALE
X
H
H
L
AOE
1
H
L
L
L
Inputs
BLE
X
H
H
L
BOE
1
H
L
L
L
BI
(0鈥?)
X
L
H
X
BO
(0鈥?)
Z
L
H
BO
0
AI
(0鈥?)
X
L
H
X
AO
(0鈥?)
Z
L
H
AO
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
AO
0
=
Previous AO before H-to-L transition of ALE
BO
0
=
Previous BO before H-to-L transition of BLE
漏 2000 Fairchild Semiconductor Corporation
DS010962
www.fairchildsemi.com
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