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SCAN182373A Datasheet

  • SCAN182373A

  • Transparent Latch with 25ohm Series Resistor Outputs

  • 12頁

  • FAIRCHILD

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SCAN182373A Transparent Latch with 25鈩?Series Resistor Outputs
January 1993
Revised August 2000
SCAN182373A
Transparent Latch with 25
鈩?/div>
Series Resistor Outputs
General Description
The SCAN182373A is a high performance BiCMOS trans-
parent latch featuring separate data inputs organized into
dual 9-bit bytes with byte-oriented latch enable and output
enable control signals. This device is compliant with IEEE
1149.1 Standard Test Access Port and Boundary-Scan
Architecture with the incorporation of the defined boundary-
scan test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),
and Test Clock (TCK).
Features
s
IEEE 1149.1 (JTAG) Compliant
s
High performance BiCMOS technology
s
25
鈩?/div>
series resistor outputs eliminate need for external
terminating resistors
s
Buffered active-low latch enable
s
3-STATE outputs for bus-oriented applications
s
25 mil pitch SSOP (Shrink Small Outline Package)
s
Includes CLAMP, IDCODE and HIGHZ instructions
s
Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
s
Power up 3-STATE for hot insert
s
Member of Fairchild鈥檚 SCAN Products
Ordering Code:
Order Number
SCAN182373ASSC
Package
Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
AI
(0鈥?)
, BI
(0鈥?)
ALE, BLE
AOE
1
, BOE
1
AO
(0鈥?)
, BO
(0鈥?)
Data Inputs
Latch Enable Inputs
3-STATE Output Enable Inputs
3-STATE Latch Outputs
Description
漏 2000 Fairchild Semiconductor Corporation
DS011544
www.fairchildsemi.com

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