Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
DESCRIPTION
The NE568A is a monolithic phase-locked loop (PLL) which
operates from 1Hz to frequencies in excess of 150MHz and features
an extended supply voltage range and a lower temperature
coefficient of the V
CO
center frequency in comparison with its
predecessor, the NE 568. The NE568A is function and
pin-compatible with the NE568, requiring only minor changes in
peripheral circuitry (see Figure 3). Temperature compensation
network is different, no resistor on Pin 12, needs to be grounded and
Pin 13 has a 3.9k鈩?resistor to ground. Timing cap, C
2
, is different
and for 70MHz operation with temperature compensation network
should be 16pF, not 34pF as was used in the NE568. The NE568A
has the following improvements: ESD protected; extended V
CC
range from 4.5V to 5.5V; operating temperature range -55 to 125擄C
(see Signetics Military 568A data sheet); less layout sensitivity; and
lower T
C
of VCO (center frequency). The integrated circuit consists
of a limiting amplifier, a current-controlled oscillator (ICO), a phase
detector, a level shift circuit, V/I and I/V converters, an output buffer,
and bias circuitry with temperature and frequency compensating
characteristics. The design of the NE568A is particularly well-suited
for demodulation of FM signals with extremely large deviation in
systems which require a highly linear output. In satellite receiver
applications with a 70MHz IF, the NE568A will demodulate
鹵20%
deviations with less than 1.0% typical non-linearity. In addition to
high linearity, the circuit has a loop filter which can be configured
with series or shunt elements to optimize loop dynamic
performance. The NE568A is available in 20-pin dual in-line and
20-pin SO (surface mounted) plastic packages.
PIN CONFIGURATION
D, N Packages
V
CC2
1
GND
2
2
GND
1
3
TCAP1
TCAP2
GND1
4
5
6
20
19
18
17
16
LF1
LF2
LF3
LF4
FREQ ADJ
15 OUT
FILT
14
V
OUT
V
CC1
7
REFBYP
PNPBYP
8
9
13 TC
ADJ2
12 TC
ADJ1
11
V
IN
INPBYP 10
TOP VIEW
SR01037
鈥?/div>
Series or shunt loop filter component capability
鈥?/div>
External loop gain control
鈥?/div>
Temperature compensated
鈥?/div>
ESD protected
1
APPLICATIONS
Figure 1. Pin Configuration
FEATURES
鈥?/div>
Operation to 150MHz
鈥?/div>
High linearity buffered output
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Small Outline Large (SOL) Package
20-Pin Plastic Dual In-Line Package (DIP)
20-Pin Plastic Small Outline Large (SOL) Package
20-Pin Plastic Dual In-Line Package (DIP)
鈥?/div>
Satellite receivers
鈥?/div>
Fiber optic video links
鈥?/div>
VHF FSK demodulators
鈥?/div>
Clock Recovery
TEMPERATURE RANGE
0 to +70擄C
0 to +70擄C
-40 to +85擄C
-40 to +85擄C
ORDER CODE
NE568AD
NE568AN
SA568AD
SA568AN
DWG #
SOT163-1
SOT146-1
SOT163-1
SOT146-1
BLOCK DIAGRAM
LF1
20
LF2
19
LF3
18
LF4
17
FREQ ADJ
16
OUT
FILT
15
V
OUT
14
TC
ADJ2
13
TC
ADJ1
12
V
IN
11
LEVEL SHIFT
OUT
BUF
TCADJ
BIAS
LEVEL SHIFT
V/I
CONVERTER
PHASE
DETECTOR
I/V
CONVERTER
AMP
NOTE:
Pins 4 and 5 can tolerate
1000V only, and all other
pins, greater than 2000V
for ESD (human body
model).
ICO
1
V
CC2
2
GND
2
3
GND
1
4
TCAP1
5
TCAP2
6
GND1
7
V
CC1
8
REFBYP
9
PNPBYP
10
INPBYP
SR01038
Figure 2. Block Diagram
1996 Feb 1
1
853-1558 16328
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