v 2 .0
54SX Family FPGAs
RadTolerant and HiRel
Fe a t ur es
Rad To ler ant 54S X Fam i ly
Hig h D ens it y De vi ces
鈥?16,000 and 32,000 Available Logic Gates
鈥?Up to 228 User I/Os
鈥?Up to 1,080 Dedicated Flip-Flops
E asy L ogi c In teg ra ti on
鈥?Tested Total Ionizing Dose (TID) Survivability Level
鈥?Radiation Performance to 100Krads (Si) (I
CC
Standby
Parametric)
鈥?Devices Available from Tested Pedigreed Lots
鈥?Up to 160 MHz On-Chip Performance
鈥?Offered as Class B and E-Flow (Actel Space Level Flow)
鈥?QMl Certified Devices
H iR el 5 4 S X F a m i ly
鈥?Non-Volatile, User Programmable
鈥?Highly Predictable Performance with 100% Automatic
Place and Route
鈥?100% Resource Utilization with 100% Pin Locking
鈥?Mixed Voltage Support鈥?.3V Operation with 5.0V Input
Tolerance for Low Power Operation
鈥?JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1
鈥?Secure Programming Technology Prevents Reverse
Engineering and Design Theft
鈥?Permanently Programmed for Operation on Power-Up
鈥?Unique In-System Diagnostic and Debug Facility with
Silicon Explorer
鈥?Supported by Actel鈥檚 Designer Series and DeskTOP Series
Development Systems with Automatic Timing Driven
Place and Route
鈥?Predictable, Reliable, and Permanent Antifuse Technology
Performance
鈥?Fastest HiRel FPGA Family Available
鈥?Up to 240 MHz On-Chip Performance
鈥?Low Cost Prototyping Vehicle for RadTolerant Devices
鈥?Offered as Commercial or Military Temperature Tested
and Class B
鈥?Cost Effective QML MIL-Temp Plastic Packaging Options
鈥?Standard Hermetic Packaging Offerings
鈥?QML Certified Devices
SX P r o du ct Pr of i l e
Device
Capacity
System Gates
Logic Gates
Logic Modules
Register Cells
Combinatorial Cells
User I/Os (Maximum)
JTAG
Packages (by pin count)
CQFP
208, 256
208, 256
208, 256
208, 256
RT54SX16
A54SX16
RT54SX32
A54SX32
24,000
16,000
1,452
528
924
179
Yes
24,000
16,000
1,452
528
924
180
Yes
48,000
32,000
2,880
1,080
1,800
227
Yes
48,000
32,000
2,880
1,080
1,800
228
Yes
March 2001
1
漏 2001 Actel Corporation