RD-19230
16-BIT MONOLITHIC TRACKING
RESOLVER-TO-DIGITAL CONVERTER
DESCRIPTION
The RD-19230 is a versatile, low cost,
state-of-the-art 16-bit monolithic Resolver-
to-Digital Converter. This single chip con-
verter offers programmable features such
as resolution, bandwidth, velocity output
scaling and encoder emulation.
Resolution programming allows selec-
tion of 10, 12, 14, or 16-bit, with accura-
cies to 2.3 min. The parallel digital data
and the internal encoder emulation sig-
nals (A QUAD B) have independent res-
olution control. Internal encoder emula-
tion will permit inhibiting (freezing) the
parallel digital data without interrupting
the A and B outputs.
The internal Synthesized Reference sec-
tion eliminates errors due to quadrature
voltage and ensures operation with a
rotor-to-stator phase shift of up to 45
degrees. The velocity output (VEL) can
be used in place of a tachometer. It has a
range of 鹵4 V relative to analog ground.
The velocity scale factor/tracking rate is
programmed with a single resistor. This
converter provides the option of using a
second set of filter components which can
be used in dual bandwidth or switch on the
fly applications.
The RD-19230 is available with operating
temperature ranges of 0擄 to +70擄C and
-40擄 to +85擄C.
FEATURES
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Accuracy up to 2.3 arc minutes
Internal Synthesized Reference
+5 Volt Only Option
Programmable Resolution,
Bandwidth and Tracking Rate
Internal Encoder Emulation with
Independent Resolution Control
Differential Resolver Input
Mode
Velocity Output Eliminates
Tachometer
Built-In-Test (BIT) Output,
No 180擄 Hangup
-40擄 to +85擄C Operating
Temperature
APPLICATIONS
With its low cost, small size, high accura-
cy, and versatile performance, the RD-
19230 converter is ideal for use in modern
high performance industrial control sys-
tems. It is ideal for users who wish to use
a resolver input in their encoder based
system. Typical applications include motor
control, machine tool control, robotics, and
process control.
Cbw
Rb
V
E
L
RH
RL BIT
V
E
L
S
J
2
Cbw/10
Rb
Cbw
Cbw/10
S
J
1
VEL2 VEL1
SHIFT
SIN
-S
+S
COS
-C
+C
VDDP
PCAP
NCAP
VSSP
A GND
VDD
GND
VSS
SYNTHESIZED
REFERENCE
-
+
CONTROL
TRANSFORMER
-
+
D1 D0
D1
-5 V
INVERTER
D0
16 BIT
UP/DOWN
COUNTER
HYSTERESIS
VCO
&
TIMING
-VCO
R CLK
R
V
GAIN
DEMODULATOR
-
+
VEL
DATA
LATCH
INTERNAL
ENCODER
EMULATION
R SET
INH
EM
EL
D1 D0
BIT 1 - BIT 16
A QUAD B A U/B
ZIP_EN
CB/ZIP
UP/DN
FIGURE 1. RD-19230 SERIES BLOCK DIAGRAM
漏
1999, 2000 Data Device Corporation
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