鈥?/div>
Minimum Timekeeping supply voltage Typ. 0.75V (Max. 1.00V); VDD pin
Low power consumption
Typ. 0.4碌A(chǔ) (Max. 1.0碌A(chǔ)) at V
DD
=3V
Built-in Backup switchover circuit (can be used for a secondary battery, or an electric double layer capacitor)
Three signal lines (CE, SCLK, and SIO) required for connection to the CPU. 路路路路路
(Maximum clock frequency of 1MHz (with V
CC
= 3V) )
Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months,
days, and weeks) (in BCD format)
Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1
month) to the CPU and provided with an interrupt flag and an interrupt halt
2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and
minute alarm settings)
Built-in voltage detector with delay
With Power-on flag to prove that the power supply starts from 0V
32-kHz clock output pin (CMOS output. 鈥淗鈥?level is always equal to VCC.)
Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
Automatic identification of leap years up to the year 2099
Selectable 12-hour and 24-hour mode settings
Built-in oscillation stabilization capacitors (CG and CD)
High precision oscillation adjustment circuit
CMOS process
Package FFP12 (2.0mm x 2.0mm x 1.0mm : R2062Kxx, SSOP16 (5.0mm x 6.4mm x 1.25mm :
R2062Sxx(Preliminary)),
1