飥?/div>
0.1 V power supply for core (V
DD
)
1.4 V to V
DD
power supply for I/O (V
DDQ
)
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR read and write operation
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
Internally self-timed write control
Clock-stop capability with 碌s restart
User programmable impedance output
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/
5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Notes: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp.
Preliminary:
The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications.
REJ03C0295-0003 Rev.0.03 Jul. 31, 2007
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