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QS5917T-100TJ Datasheet

  • QS5917T-100TJ

  • LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

  • 7頁

  • IDT

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QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FEATURES:
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QS5917T
5V operation
2xQ output, Q/2 output, Q output
Outputs tri-state while
RST
low
Internal loop filter RC network
Low noise TTL level outputs
< 500ps output skew, Q
0
-Q
4
PLL disable feature for low frequency testing
Balanced Drive Outputs 鹵 24mA
132MHz maximum frequency (2xQ output)
Functional equivalent to Motorola MC88915
ESD > 2000V
Latch-up > 鈥?00mA
Available in QSOP and PLCC packages
DESCRIPTION
The QS5917T Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight
outputs are available: Q
0
-Q
4
, 2xQ, Q/2, Q
5
. Careful layout and design
insures < 500ps skew between the Q
0
-Q
4
, and Q/2 outputs. The QS5917T
includes an internal RC filter which provides excellent jitter characteris-
tics and eliminates the need for external components. In addition, TTL
level outputs reduce clock signal noise. Various combinations of feed-
back and a divide-by-2 in the VCO path allow applications to be custom-
ized for linear VCO operation over a wide range of input SYNC fre-
quencies. The VCO can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5917T is designed for use in
high-performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distri-
bution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LOCK
FEEDBACK
PLL_EN
FREQ_SEL
SYNC
0
SYNC
1
RST
0
0
1
PHASE
DETECTOR
LOOP
FILTER
1
VCO
1
/2
0
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
Q
Q/2
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
2xQ
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2000 Integrated Device Technology, Inc.
JULY 2000
DSC-5227/2

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