鈥?/div>
20 output, low skew clock signal buffer
High drive FCT-type outputs
Reduced swing TTL outputs for low noise
Input hysteresis for better noise margin
Monitor output
Guaranteed low skew
鈥?0.5ns output skew
鈥?0.7ns pulse skew
鈥?1ns part-to-part skew
Available in 40-pin QVSOP
QS5820T
DESCRIPTION:
The QS5820T clock driver/buffer circuits can be used for clock distri-
bution schemes where low skew, high speed, and small footprint are
primary concerns. The QS5820T offers four banks of five non-inverting
outputs. Designed in IDT's proprietary QCMOS process, this device
provides low propagation delay buffering with on-chip skew of 0.5ns for
same-transition, same-bank signals. The QS5820T provides major skew
advantages over octal type devices where total part-to-part skew (t
SK(t)
)
of >1ns is unacceptable. Furthermore, board area consumed by the
QVSOP package is almost one-third that of the typical SOIC package
offered for octal devices. This clock buffer product is designed for use in
high performance workstation, multi-board computing and telecommuni-
cations systems. The QS5820T is available in the 40-pin QVSOP pack-
age which offers the world鈥檚 smallest logic footprint.
鈥?/div>
FUNCTIONAL BLOCK DIAGRAM
OE A
5
IN A
OA
1
-O A
5
OE B
5
IN B
OB
1
-O B
5
MONB
OEC
5
INC
OC
1
-OC
5
OED
5
IND
OD
1
-OD
5
MO ND
COMMERCIAL TEMPERATURE RANGE
1
c
2000
Integrated Device Technology, Inc.
DECEMBER 2000
DSC-5822/-
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