鈥?/div>
1ns part-to-part skew
Input hysteresis for better noise margin
Monitor output
Undershoot clamp diodes on all inputs
Std., A, and B speed grades
Available in QSOP and SOIC packages
QS5805T/AT/BT
DESCRIPTION:
The QS5805T clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of five non-inverting outputs. This device provides low propagation delay
buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS5805T is characterized for operation at -40擄C to +85擄C.
鈭?/div>
鈭?/div>
鈭?/div>
鈭?/div>
鈭?/div>
FUNCTIONAL BLOCK DIAGRAM
OE
A
5
IN
A
OA
5
OA
1
MON
5
IN
B
OB
5
OB
1
OE
B
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
JULY 2000
DSC-5267
QS5805TSO相關(guān)型號(hào)PDF文件下載
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英文版
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