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QS532807 Datasheet

  • QS532807

  • GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

  • 6頁(yè)

  • IDT

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QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FEATURES:
鈭?/div>
鈭?/div>
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鈭?/div>
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JEDEC compatible LVTTL level
10 low skew clock outputs
Clock input is 5V tolerant
Pinout and function compatible with QS5807
25鈩?on-chip resistors available for low noise
Input hysteresis for better noise margin
Guaranteed low skew:
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0.35ns output skew (same bank)
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0.6ns output skew (different bank)
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0.75ns part-to-part skew
Available in QSOP and SOIC packages
QS532807
DESCRIPTION:
The QS532807 clock driver/buffer circuit can be used for clock
buffering schemes where low skew is a key parameter. The QS532807
offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS
process, these devices provide low propagation delay buffering with on-
chip skew of 0.35ns for same-transition, same bank signals. The
QS532807 has on-chip series termination resistors for lower noise clock
signals. The QS532807 series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise
sensitive clock distribution circuits. These clock buffer products are
designed for use in high-performance workstations, embedded and
personal computing systems. Several devices can be used in parallel
or scattered throughout a system for guaranteed low skew, system-wide
clock distribution networks.
鈭?/div>
FUNCTIONAL BLOCK DIAGRAM
O
1
O
2
O
3
O
4
O
5
IN
O
6
O
7
O
8
O
9
O
10
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC - 5848

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