QL8X12B
pASIC
廬
1 Family
Very-High-Speed CMOS FPGA
Rev B
pASIC
HIGHLIGHTS
Very High Speed
鈥?ViaLink
廬
metal-to-metal programmable鈥搗ia
antifuse technology, allows counter speeds over 150 MHz and logic
cell delays of under 2 ns.
High Usable Density
鈥?An 8-by-12 array of 96 logic cells provides
1,000 usable ASIC gates (2,000 PLD gates) in 44-pin and 68-pin
PLCC, and 100-pin TQFP packages.
Low-Power, High-Output Drive
鈥?Standby current typically 2 mA.
A 16-bit counter operating at 100 MHz consumes less than 50 mA.
Minimum IOL of 12 mA and IOH of 8 mA
Low-Cost, Easy-to-Use Design Tools
鈥?Designs entered and
simulated using QuickLogic's new QuickWorks
廬
development
environment, or with third-party CAE tools including Viewlogic,
Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place
and route on PC and workstation platforms using QuickLogic
software.
鈥?,000
usable ASIC gates,
64 I/O pins
4
pASIC 1
QL8x12B
Block Diagram
96 Logic Cells
= Up to 56 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
4-5