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QL7180-6PB516I Datasheet

  • QL7180-6PB516I

  • USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|516PIN

  • 26頁

  • ETC

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QL7180 DSP Data Sheet
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Combining Embedded DSP Blocks, Performance, Density
and Embedded RAM
1.0 Device Highlights
Clock Network
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9 global clock networks
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1 dedicated, 8 programmable
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16 I/O (high drive) networks:
High Speed Customizable Logic
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0.25u, 5 layer metal CMOS process
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2.5 V Vcc, 2.5 / 3.3 V drive capable I/O
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512 programmable I/O
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4,032 Logic Cells
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660,000 max system gates
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Muxed based architecture,
2 banks per I/O
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20 Quad-net networks: 5 per quadrant
Programmable I/O
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High performance enhanced I/O:
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less than 3 ns Tco
Programmable slew rate control
Programmable I/O standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
8 independent I/O banks
3 register configuration: Input, Output, OE
non-volatile technology
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Completely customizable for any
digital applications
Dual Port SRAM
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36 blocks of dual-port SRAM
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2,304 bit dual port high performance
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Parameterized IP
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Free parameterized IP administered with a
DSP Wizard
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Supports multiple and hierarchical IP
instantiations
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SRAM Blocks
Total of 82,900 bits
RAM / ROM / FIFO Wizard for automatic
configuration
Configurable and cascadable
Array sizes of 2, 4, 9, and 18
< 3 ns access times, 300+ MHz FIFO
Applications
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Signal processing operators
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Signal processing functions
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Networking / communications for VoIP
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Speech / voice processing
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Channel coding
Figure 1: Embedded QuickDSP Block Diagram
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QL7180 QuickDSP
TM
Data Sheet Rev B
1

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