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QL6250PS484 Datasheet

  • QL6250PS484

  • ASIC

  • 164.63KB

  • 13頁

  • ETC

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Eclipse Family Data Sheet
鈥?鈥?鈥?鈥?鈥?鈥?/div>
Combining Performance, Density and Embedded RAM
1.0 Device Highlights
Flexible Programmable Logic
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.25u, 5 layer metal CMOS process
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2.5 V Vcc, 2.5/3.3 V drive capable I/O
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Up to 4032 SuperCells
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Up to 583,000 Max System Gates
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Up to 512 I/O
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Programmable I/O
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High performance Enhanced I/O (EIO):
Embedded Dual Port SRAM
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Up to 36-2,304 bit Dual Port High
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performance SRAM Blocks
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Up to 82,900 RAM bits
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RAM/ROM/FIFO Wizard for automatic
Less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
8 Independent I/O Banks
3 Register Configuration: Input, Output, OE
Advanced Clock Network
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9 Global Clock Networks
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1 dedicated
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8 programmable
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16 I/O (high drive) Networks:
configuration
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Configurable and Cascadable
Applications
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Signal processing operators
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Signal processing functions
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Networking / communications for VoIP
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Speech / voice processing
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Channel coding
2 I/O鈥檚 per bank
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20 Quad-Net Networks: 5 per quadrant
Figure 1: Embedded Eclipse Block Diagram
Eclipse
TM
Family Data Sheet
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1

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