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QL5432 - Enhanced QuickPCI

TM

Device

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

last updated 2/5/01

QL5432 - Enhanced QL5232

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PCI Bus 鈥?33 MHz 32 bits (data and address)

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Supports all PCI commands (including configuration

and MWI)

Supports fully-customizable byte enables as a master

Zero-wait-state write and one-wait-state read target

interface

Supports all types of PCI target terminations: disconnect

with data transfer, disconnect without data transfer,

and retry

Supports target aborts

Has 125 more logic cells in FPGA section, but 2 less

RAM blocks

Pin Compatible with QL5232

PCI CONTROLLER

MASTER

CONTROLLER

HIGH

SPEED

DATA

PATH

TARGET

CONTROLLER

32

INTERFACE

266 User I/O

160

MHz

FIFOs

High Speed

Logic Cells

Config

Space

DMA

Controller

PROGRAMMABLE LOGIC

Device Highlights

High Performance PCI Controller

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FIGURE 1. QL5432 Diagram

Extendable PCI Functionality

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32-bit / 33 MHz PCI Master/Target

Zero-wait state PCI Master provides 132 MB/s

transfer rates

Zero-wait-state PCI Target Write/One-wait-state PCI

Target Read interface

Supports all PCI commands, including configuration

and MWI

Supports fully-customizable byte enable for master

channels

Target interface supports retry, disconnect with/without

data transfer, and target abort

Programmable back-end interface to optional local

processor

Independent PCI bus (33 MHz) and local bus

(up to 160 MHz) clocks

Fully customizable PCI Configuration Space

Configurable FIFOs with depths up to 256

Reference design with driver code (Win 95/98/

Win 2000/NT4.0) available

PCI v2.2 compliant

Supports Type 0 Configuration Cycles in Target mode

3.3V, 5V Tolerant PCI signaling supports Universal

PCI Adapter designs

3.3V CMOS in 208-pin PQFP and 456-pin PBGA

Supports endian conversions

Unlimited/Continuous Burst Transfers supported

Support for PCI host-bridge function

Support for Configuration Space from 0x40 to 0x3FF

Multi-Function, Expanded Capabilities, & Expansion

ROM capable

Power management, Compact PCI, hot-swap/

hot-plug compatible

PCI v2.2 Power Management Spec compatible

PCI v2.2 Vital Product Data (VPD) configuration support

Programmable Interrupt Generator

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O support with local processor

Mailbox register support

Programmable Logic

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1427 Logic Cells

23,040 RAM bits, up to 266 I/O pins

250 MHz 16-bit counters, 275 MHz Datapaths, 160

MHz FIFOs

All back-end interface and glue-logic can be implemented

on chip

Any combination of FIFOs that require 20 or less

QuickLogic RAM Modules

Six 32-bit busses interface between the PCI Controller

and the Programmable Logic

Rev A

next

QL5432-33APQ208I相關(guān)型號(hào)PDF文件下載

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  QL5432-33APQ208C
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