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QL3040-3PQ208I Datasheet

  • QL3040-3PQ208I

  • FPGA|1008-CELL|CMOS|QFP|208PIN|PLASTIC

  • 19頁

  • ETC

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QL3040 pASIC 3 FPGA Data Sheet
鈥⑩€⑩€⑩€⑩€⑩€?/div>
40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
鈥?/div>
40,000 Usable PLD Gates with 252 I/Os
鈥?/div>
300 MHz 16-bit Counters,
Eight Low-Skew Distributed
Networks
鈥?/div>
Two array clock/control networks available
400 MHz Datapaths
鈥?/div>
0.35
碌m
four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
鈥?/div>
100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset
inputs 鈥?each driven by an input-only pin
鈥?/div>
Six global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control 鈥?each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
complete pin-out stability
鈥?/div>
Variable-grain logic cells provide high
performance and 100% utilization
鈥?/div>
Comprehensive design tools include high
quality Verilog/VHDL synthesis
High Performance
鈥?/div>
Input + logic cell + output total delays
under 6 ns
鈥?/div>
Data path speeds over 400 MHz
鈥?/div>
Counter speeds over 300 MHz
Advanced I/O Capabilities
鈥?/div>
Interfaces with both 3.3 V and 5.0 V devices
鈥?/div>
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
鈥?/div>
Full JTAG boundary scan
鈥?/div>
I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 252 I/O Pins
鈥?/div>
244 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
鈥?/div>
Eight high-drive input/distributed
network pins
Figure 1: 1,008 pASIC 3 Logic Cells
漏 2002 QuickLogic Corporation
www.quicklogic.com
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1

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