QL3012 - pASIC 3 FPGA
TM
12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and
High Density
QL3012 - pASIC 3 FPGA
D
EVICE
H
IGHLIGHTS
Device Highlights
High Performance & High Density
s
12,000 Usable PLD Gates with 118 I/Os
s
16-bit counter speeds over 300 MHz, data path speeds over
400 MHz
s
0.35um four-layer metal non-volatile CMOS process for
smallest die sizes
Easy to Use / Fast Development Cycles
s
100% routable with 100% utilization and complete
pin-out stability
s
Variable-grain logic cells provide high performance and
100% utilization
s
Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilites
s
Interfaces with both 3.3 volt and 5.0 volt devices
s
PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4
FIGURE 1. 320 Logic Cells
speed grades
s
Full JTAG boundary scan
s
Registered I/O cells with individually controlled clocks and
P
RODUCT
S
UMMARY
Product Summary
output enables
Total of 118 I/O Pins
s
110 bidirectional input/output pins, PCI-compliant for 5.0 volt
and 3.3 volt buses for -1/-2/-3/-4 speed grades
s
4 high-drive input-only pins
s
4 high-drive input/distributed network pins
The QL3012 is a 12,000 usable PLD gate member of
the pASIC 3 family of FPGAs. pASIC 3 FPGAs are
fabricated on a 0.35mm four-layer metal process
using QuickLogic鈥檚 patented ViaLink technology to
provide a unique combination of high performance,
high density, low cost, and extreme ease-of-use.
The QL3012 contains 320 logic cells. With a
maximum of 118 I/Os, the QL3012 is available in
84-pin PLCC, 100-pin TQFP, and 144-pin TQFP
packages.
Software support for the complete pASIC 3 family,
including the QL3012, is available through three basic
packages. The turnkey QuickWorks鈥?package
provides the most complete FPGA software solution
from design entry to logic synthesis, to place and
route, to simulation. The QuickTools
TM
for
Workstations package provides a solution for
designers who use Cadence, Exemplar, Mentor,
Synopsys, Synplicity, Viewlogic, Veribest, or other
third-party tools for design entry, synthesis, or
simulation.
Four Low-Skew Distributed Networks
s
Two array clock/control networks available to the logic cell flip-
flop clock, set and reset inputs - each driven by an input-only pin
s
Six global clock/control networks available to the logic cell F1,
clock set and reset inputs and the input and I/O register clock,
reset and enable inputs as well as the output enable control - each
driven by an input-only or I/O pin, or any logic cell output or I/O
cell feedback
High Performance
s
Input + logic cell + output total delays under 6 ns
s
Data path speeds over 400 MHz
s
Counter speeds over 300 MHz
QL3012 Rev C
7-19
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