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QL2003-1PF100I Datasheet

  • QL2003-1PF100I

  • Field Programmable Gate Array (FPGA)

  • 184.25KB

  • 10頁(yè)

  • ETC

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3.3V and 5.0V pASIC 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
廬
QL2003
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency
and
performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
鈥?3,000
usable ASIC gates,
118 I/O pins
-16-bit counter speeds exceeding 200 MHz
-3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
-3-layer metal ViaLink
廬
process for small die sizes
-100% routable and pin-out maintainable
3
pASIC 2
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
QL2003
Block Diagram
192
Logic
Cells
3-5

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