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QL12X16B-2PF100C Datasheet

  • QL12X16B-2PF100C

  • Field Programmable Gate Array (FPGA)

  • 8頁

  • ETC

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QL12X16B
pASIC
廬
1 Family
Very-High-Speed CMOS FPGA
Rev C
pASIC
HIGHLIGHTS
Very High Speed
鈥?ViaLink
廬
metal-to-metal programmable鈥搗ia
antifuse technology, allows counter speeds over 150 MHz and logic
cell delays of under 2 ns.
High Usable Density
鈥?A 12-by-16 array of 192 logic cells
provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and
84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages.
Low-Power, High-Output Drive
鈥?Standby current typically 2
mA. A 16-bit counter operating at 100 MHz consumes less than 50
mA. Minimum IOL of 12 mA and IOH of 8 mA
Low-Cost, Easy-to-Use Design Tools
鈥?Designs entered and
simulated using QuickLogic's new QuickWorks
廬
development
environment, or with third-party CAE tools including Viewlogic,
Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place
and route on PC and workstation platforms using QuickLogic
software.
鈥?,000
usable ASIC gates,
88 I/O pins
4
pASIC 1
QL12x16B
Block Diagram
192 Logic Cells
= Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
4-13

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