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Q67100-Q2021 Datasheet

  • Q67100-Q2021

  • 256k x 16-Bit Dynamic RAM

  • 183.78KB

  • 23頁

  • INFINEON   INFINEON

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256k
脳
16-Bit Dynamic RAM
HYB 514171BJ-50/-60
Advanced Information
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262 144 words by 16-bit organization
0 to 70
擄C
operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
CAS access time:
15ns (-50, -60 version)
Cycle time:
95 ns (-50 version)
110 ns (-60 version)
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
Single + 5.0 V (鹵 10 %) supply with a
built-in VBB generator
Low Power dissipation
max. 1045 mW active (-50 version)
max. 935 mW active (-60 version)
鈥?Standby power dissipation
11 mW standby (TTL)
5.5 mW max. standby (CMOS)
鈥?Output unlatched at cycle end allows
two-dimensional chip selection
鈥?Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and fast page
mode capability
鈥?2 CAS / 1 WE control
鈥?All inputs and outputs TTL-compatible
鈥?512 refresh cycles / 16 ms
鈥?Plastic Packages:
P-SOJ-40-1 400 mil width
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The HYB 514171BJ is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The
HYB 514171BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514171BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include single + 5 V (鹵 10 %)
power supply, direct interfacing with high performance logic device families such as Schottky TTL.
Semiconductor Group
1
1998-10-01

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