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Q67100-Q2072 Datasheet

  • Q67100-Q2072

  • 256k x 16-Bit EDO-DRAM

  • 180.10KB

  • 22頁

  • INFINEON   INFINEON

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256k
脳
16-Bit EDO-DRAM
HYB 514175BJ-50/-55/-60
Advanced Information
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
262 144 words by 16-bit organization
0 to 70
擄C
operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)
鈥?Low Power dissipation
max. 1100 mW active (-50 version)
max. 1045 mW active (-55 version)
max. 935 mW active (-60 version)
鈥?Standby power dissipation
11 mW standby (TTL)
5.5 mW max. standby (CMOS)
鈥?Output unlatched at cycle end allows
two-dimensional chip selection
鈥?Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and hyper page
(EDO) mode capability
鈥?2 CAS/1 WE control
鈥?All inputs and outputs TTL-compatible
鈥?512 refresh cycles/16 ms
鈥?Plastic Packages:
P-SOJ-40-1 400 mil width
鈥?CAS access time:
13 ns (-50 & -55 version)
15 ns (-60 version)
鈥?Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)
鈥?Hyper page mode (EDO) cycle time
20 ns (-50 & -55 version)
25 ns (-60 version)
鈥?High data rate
50 MHz (-50 & -55 version)
40 MHz (-60 version)
鈥?Single + 5 V (鹵 10 %) supply with a built-in
V
BB
generator
Semiconductor Group
1
1998-10-01

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