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Q67100-Q1841 Datasheet

  • Q67100-Q1841

  • 64-MBit Synchronous DRAM

  • 410.25KB

  • 53頁

  • INFINEON   INFINEON

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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
64-MBit Synchronous DRAM
鈥?High Performance:
鈥?Multiple Burst Read with Single Write
Operation
Units
MHz
ns
ns
ns
ns
鈥?Automatic and Controlled Precharge
Command
鈥?Data Mask for Read/Write Control (x4, x8)
鈥?Data Mask for Byte Control (x16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Suspend Mode and Power Down Mode
鈥?4096 Refresh Cycles / 64 ms
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL Interface
鈥?Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
鈥?-7.5 version for PC133 3-3-3 application
-8 version for PC100 2-2-2 applications
-7.5
-8
125
8
6
10
6
f
CKMAX
t
CK3
t
AC3
t
CK2
t
AC2
133
7.5
5.4
10
6
鈥?Fully Synchronous to Positive Clock Edge
鈥?0 to 70
擄C
operating temperature
鈥?Four Banks controlled by BA0 & BA1
鈥?Programmable CAS Latency: 2, 3
鈥?Programmable Wrap Sequence: Sequential
or Interleave
鈥?Programmable Burst Length: 1, 2, 4, 8
鈥?Full page (optional) for sequential wrap
around
The HYB 39S64400/800/160BT are four bank Synchronous DRAM鈥檚 organized as
4 banks
脳
4MBit
脳4,
4 banks
脳
2 MBit
脳8
and 4 banks
脳
1 Mbit
脳16
respectively. These synchron-
ous devices achieve high speed data transfer rates by employing a chip architecture that prefects
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.2
碌m
64 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for Synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
鹵
0.3 V power supply and are available in TSOPII packages.
Data Book
1
12.99

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