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Q67100-Q1327 Datasheet

  • Q67100-Q1327

  • 16 MBit Synchronous DRAM

  • 22頁

  • INFINEON   INFINEON

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16 MBit Synchronous DRAM
(second generation)
Advanced Information
鈥?High Performance:
CAS latency = 3
-8
125
8
7
-10
100
10
8
Units
MHz
ns
ns
HYB 39S16400/800/160AT-8/-10
鈥?Multiple Burst Read with Single Write
Operation
鈥?Automatic and Controlled Precharge
Command
鈥?Data Mask for Read/Write control (脳 4,
脳
8)
鈥?Dual Data Mask for byte control (脳 16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Suspend Mode and Power Down Mode
鈥?4096 refresh cycles/64 ms
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL Interface versions
鈥?Plastic Packages:
P-TSOPII-44-1 400 mil width (脳 4,
脳
8)
P-TSOPII-50-1 400 mil width (脳 16)
f
CK
t
CK3
t
AC3
鈥?Single Pulsed RAS Interface
鈥?Fully Synchronous to Positive Clock Edge
鈥?0 to 70
擄C
operating temperature
鈥?Dual Banks controlled by A11 (Bank Select)
鈥?Programmable CAS Latency: 1, 2, 3
鈥?Programmable Wrap Sequence: Sequential
or Interleave
鈥?Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential type
1, 2, 4, 8 for Interleave type
The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM鈥檚 based on the die revisions 鈥淏鈥?/div>
and 鈥淐鈥?and organized as 2 banks
脳
2 MBit
脳
4, 2 banks
脳
1 MBit
脳
8 and 2 banks
脳
512 kBit
脳
16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V
鹵
0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01

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