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Q67100-H9036 Datasheet

  • Q67100-H9036

  • Nonvolatile Memory 2-Kbit E2PROM with I2C Bus Interface with...

  • 235.29KB

  • 10頁(yè)

  • INFINEON   INFINEON

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Nonvolatile Memory
2-Kbit E
2
PROM with
I
2
C Bus Interface
with Extended Temperature Range
Features
q
Word-organized reprogrammable nonvolatile memory
2
in n-channel floating-gate technology (E PROM)
q
256
脳
8-bit organization
q
+ 5 V supply voltage
2
q
Serial 2-line bus for data input and output (I C Bus)
q
Reprogramming mode, typ. 15 ms erase/write cycle
q
Reprogramming by means of on-chip control
(without external control)
q
Data retention longer than 10 years
5
q
More than 10 reprogramming cycles
per address
q
Extended temperature range from 鈥?40 to 110
擄C
SDE 2526
MOS IC
P-DIP-8-4
P-DSO-8-1
Type
SDE 2526-5
SDE 2526-5 A2G
SDE 25X26 A2
SDE 25X26-5 A2G
Circuit Description
I
2
C Bus Interface
The
I
2
C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to
V
CC
(open drain output stage).
The possible operational states of the
I
2
C Bus are shown in
figure 1.
In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
Ordering Code
Q67100-H9020
Q67100-H9036
Q67100-H3261
Q67100-H3262
Package
P-DIP-8-4
P-DSO-8-1 (SMD)
P-DIP-8-4
P-DSO-8-1 (SMD)
Pin Configuration
SIEMENS
SIEMENS
STANDARD
STANDARD
Semiconductor Group
82
01.96

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