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PUMA68S4000M-025 Datasheet

  • PUMA68S4000M-025

  • SRAM|128KX32|CMOS|LDCC|68PIN|CERAMIC

  • 9頁(yè)

  • ETC

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128K x 32 SRAM MODULE
PUMA 68S4000/A - 020/025/35/45
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel.+44 (0191) 2930500 Fax.+44 (0191) 2590997
Issue 4.5 : April 2001
Description
The PUMA68S4000/A is a 4Mbit CMOS High
Speed Static RAM organised as 128K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 20, 25, 35, and 45ns. The output
width is user configurable as 8 , 16 or 32 bits using
four Chip Selects (CS1~4).
The device features multiple ground pins for
maximum noise immunity and TTL compatible
inputs and outputs. The PUMA 68S4000/A offers a
dramatic space saving advantage over four
standard 128Kx8 devices.
Features
鈥?Fast Access Times of 20 ,25, 35 and 45 ns.
鈥?JEDEC 68 'J' leaded plastic surface mount Substrate
鈥?Industrial or Military Grade.
鈥?Upgradeable footprint.
鈥?User Configurable as 8 / 16 / 32 bit wide output.
鈥?Operating Power
Low Power Standby
鈥?Fully Static operation.
鈥?Multiple ground pins for maximum noise immunity.
鈥?Single 5V鹵10% Power supply.
(32-BIT)
(TTL)
4.00 W (Max)
1.43 W (Max)
Block Diagram
(PUMA 68 S4000A page 2)
A0-A16
OE
WE
Pin Definition
(PUMA 68 S4000A page 2)
CS3
GND
CS4
NC
A0
WE
A6
A7
A8
A2
A1
A3
A4
A5
VCC
A10
A9
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
PUMA 68S4000
VIEW
FROM
ABOVE
55
54
53
52
51
50
49
48
47
46
45
44
CS1
CS2
A11
NC
GND
VCC
NC
NC
NC
OE
NC
A12
A13
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A16
D0 - D31
CS1~4
WE1~4
OE
NC
V
CC
GND
Package Details
Plastic 68 J-Leaded JEDEC PLCC
A14
A15
A16
NC

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