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PUMA67E4001I-15 Datasheet

  • PUMA67E4001I-15

  • EEPROM|128KX32|CMOS|LDCC|68PIN|CERAMIC

  • 15頁

  • ETC

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128K x 32 EEPROM Module
PUMA 2/67E4001/A/B -12/15/20
Elm Road, West Chirton, North Shields, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 4.3 : January 2001
Description
Available in PGA (Puma 2), and JLCC (Puma 67)
footprints, the Puma **E4001 is a 4 Mbit EEPROM
module user configurable as 128K x 32, 256K x 16
or 512K x 8. Available with access times of 120, 150
and 200ns, the device features hardware and software
data protection, 10,000 cycle Write/Erase capability
and 10 year data retention time.
Several pinout variants of the PUMA67 are available
including single and multiple WE variants.
Parts may be screened in accordance with MIL-STD-
883
Features
鈥?4 Megabit EEPROM module.
鈥?Access Times of 120/150/200 ns.
鈥?Output Configurable as 32/ 16/ 8 bit wide.
鈥?Upgradeable footprint
鈥?Operating Power 1600/ 830/ 445 mW (Max).
Low Power Standby
2.2 mW (Max).
鈥?Byte and Page Write (128 Bytes) in 5ms typical with
DATA Polling and Toggle bit indication of end of
Write.
鈥?Hardware and Software Data Protection.
鈥?Puma 2 - 66 pin Ceramic PGA.
鈥?Puma 67 - 68 Lead Ceramic JLCC.
鈥?May be screened in accordance with MIL-STD-883.
鈥?100,000 W/E cycle endurance option
Block Diagram
PUMA 2E4001, 67E4001A and 67E4001B
Block Diagram
PUMA 67E4001A/B
A0~A16
OE
WE4
WE3
WE2
WE1
A0~A16
OE
WE
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
Pin Functions
A0~A16
CS1~4
OE
GND
Address Input
Chip Select
Output Enable
Ground
D0~D31
WE1~4
Vcc
Data Inputs/Outputs
Write Enables
Power (+5V)

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