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PUMA67S4000MB-35 Datasheet

  • PUMA67S4000MB-35

  • SRAM|128KX32|CMOS|LDCC|68PIN|CERAMIC

  • 10頁(yè)

  • ETC

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128K x 32 SRAM Module
PUMA 2/67S4000/A-020/025/35
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 4.4 : April 2001
Description
Available in PGA (PUMA 2) and JLCC (PUMA 67)
footprints the PUMA **S4000 is a 4 Mbit SRAM
module, user configurable as 128K x 32, 256K x 16
or 512K x 8. The device is available with fast access
times of 20, 25 and 35ns and may be screened in
accordance with MIL-STD-883C.
Features
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4 Megabit SRAM module.
Fast Access Times of 20/25/35 ns.
Output Configurable as 32 / 16 / 8 bit wide.
Upgradeable footprint.
Operating Power 3740 / 2310 / 1595 mW (Max).
Low Power Standby 880 mW (Max).
TTL Compatible Inputs and Outputs.
May be screened in accordance with MIL-STD-883.
PUMA 2 - 66 pin ceramic PGA.
PUMA 67 - 68 pin ceramic JLCC.
Block Diagram
PUMA 2S4000, 67S4000A, 67S4000B
A0~A16
OE
WE4
WE3
WE2
WE1
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Block Diagram
PUMA 67S4000
A0-A16
OE
WE
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Pin Functions
A0~A16
CS1~4
OE
GND
Address Input
Chip Select
Output Enable
Ground
D0~D31
WE1~4
Vcc
Data Inputs/Outputs
Write Enables
Power (+5V)

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