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PUMA2S1000L-025 Datasheet

  • PUMA2S1000L-025

  • SRAM|32KX32|CMOS|PGA|66PIN|CERAMIC

  • 170.15KB

  • 9頁(yè)

  • ETC

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32K x 32 SRAM MODULE
PUMA 2S1000 - 020/025/35/45
Elm Road, West Chirton, North Shields, Tyne and Wear, NE29 8SE
England, Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 4.4 : April 2001
Description
The PUMA 2S1000 is a 1Mbit high speed static RAM
organised as 32K x 32 in a 66 pin ceramic PGA
package. Access times of 20ns, 25ns, 35ns or 45ns
are available. The device has a user configurable
output width by 8 ,16 or 32 bits, and features a low
power standby mode with 3.0V battery back-up
capability. The package includes on board
decoupling capacitors and is suitable for thermal
ladder operations.
It may be screened in accordance with
MIL-STD-883.
1,048,576 bit CMOS High Speed Static RAM
Features
鈥?Very Fast Access times of 20/25/35/45 ns.
鈥?User Configurable as 8 / 16 / 32 bit wide output.
鈥?Operating Power
1.6 W (max) 8 bit
鈥?Low Power Standby 44 mW (max) - L Version
鈥?Upgradeable Package.
鈥?Package Suitable for Thermal Ladder Applications.
鈥?On board decoupling capacitors.
鈥?Low voltage data retention.
鈥?May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definition
1
A0~A14
OE
WE4
WE3
WE2
WE1
12
WE2
13
CS2
14
GND
15
D11
16
A10
17
A11
18
A12
19
VCC
20
CS1
21
NC
22
D3
23
D15
24
D14
25
D13
26
D12
27
OE
28
NC
29
WE1
30
D7
31
D6
32
D5
33
D4
34
D24
35
D25
36
D26
37
45
VCC
46
CS4
47
WE4
48
D27
49
A3
50
A4
51
A5
52
WE3
53
CS3
54
GND
55
D19
56
D31
57
D30
58
D29
59
D28
60
A0
61
A1
62
A2
63
D23
64
D22
65
D21
66
D20
D8
2
D9
3
D10
4
A13
5
A14
6
NC
7
NC
8
NC
9
D0
10
D1
11
D2
32Kx8
SRAM
CS1
CS2
CS3
CS4
D0~D7
D8~D15
D16~D23
D24~D31
32Kx8
SRAM
32Kx8
SRAM
32Kx8
SRAM
VIEW
FROM
ABOVE
A6
38
A7
39
NC
40
A8
41
A9
42
D16
43
D17
44
D18
Pin Functions
A0~A14
CS1~4
WE1~4
V
CC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0~D31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground

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