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PT5062N Datasheet

  • PT5062N

  • Analog IC

  • 4頁

  • ETC

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PT5060 Series
9-W +5V-Input Dual-Output
Integrated Switching Regulator
SLTS027B
(Revised 12/19/2001)
Features
鈥?/div>
Single Device: +5V Input
鈥?/div>
Complimentary Dual Output:
鹵12V, 鹵15V
鈥?/div>
Wide Input Voltage Range
鈥?/div>
85% Efficiency
鈥?/div>
Adjustable Output Voltage
鈥?/div>
Laser-trimmed
Description
The PT5060 series of dual-output
Integrated Switching Regulators (ISRs)
provide a complimentary 鹵12V or 鹵15V
from a single +5V input. Applications
include systems that require power for
analog interface circuitry, such as D/A
and A/D converters, and Op Amps. The
output voltage can be adjusted with an
external resistor. These ISRs are made
available in a 12-pin single in-line pin
(SIP) package. Note that these modules
are are not short-circuit protected.
Pin-Out Information
Pin
Function
鈥揤o
2
GND
V
in
V
in
V
in
GND
GND
+Vo
1
+Vo
1
+Vo
1
V
o
Adj
Do Not Connect
Ordering Information
PT5061簍
= 鹵12 Volts
PT5062簍
= 鹵15 Volts
Standard Application
V
o
adj
11
1
1
2
3
4
鈥揤 o
2
+Vo
1
PT Series Suffix
(PT1234
x
)
Case/Pin
Configuration
Vertical
Horizontal
SMD
Vertical, Side Tabs
Horizontal, Side Tabs
SMD, Side Tabs
Order
Suffix
Package
Code *
(ECD)
(ECA)
(ECC)
(ECE)
(ECG)
(ECK)
V in
3,4,5
5
6
7
8
9
PT5060
2,6,7
8,9,10
C
1
100
碌F
COM
+
COM
10
11
12
N
A
C
R
G
B
* Previously known as package style 300.
(Reference the applicable package code drawing
for the dimensions and PC board layout)
C
1
= Required 100碌F electrolytic
Specifications
Characteristics
Output Current
(Unless otherwise stated, T
a
=25擄C, V
in
=+5V, I
o
=I
o
max, C
1
=100碌F)
PT5060 SERIES
Symbol
I
o
Conditions
Over V
in
range
Vo
1
= +12V
Vo
2
= 鈥?2V
Vo
1
= +15V
Vo
2
= 鈥?5V
Current Limit
Inrush Current
Input Voltage Range
Output Voltage Tolerance
Line Regulation
Load Regulation
V
o
Ripple (pk-pk)
Transient Response
Efficiency
Switching Frequency
Operating Temperature Range
Storage Temperature
Mechanical Shock
Mechanical Vibration
Weight
Notes:
(1)
(2)
(3)
(4)
Do not operate thes negative output rail of these ISRs below the minimum load.
ISRs based on a boost topology are not short-circuit protected.
The inrush current stated is above the normal input current for the associated output load.
See Safe Operating Area curves or consult the factory for the appropriate derating.
I
lim
I
ir
t
tr
V
in
鈭哣
o
Reg
line
Reg
load
V
n
t
tr
V
os
s
T
a
T
s
Per Mil-STD-883D, Method 2002.3,
1 msec, Half Sine, mounted to a fixture
Per Mil-STD-883D, Method 2007.2
20-2000 Hz, Soldered in a PC board
鈥?/div>
鈥?/div>
On start up
Over I
o
range
Over V
in
and I
o
ranges
T
a
= 0擄C to SOA limit
(3)
Over V
in
range
0.1
鈮?/div>
I
o
鈮?/div>
I
o
max
20MHz bandwidth
25% load change
V
o
over/undershoot
I
o
=0.2A each output
Over V
in
and I
o
ranges
鈥?/div>
+Vo
1
鈥揤o
2
+Vo
1
鈥揤o
2
Min
0.05
0.05
(1)
0.05
0.05
(1)
鈥?/div>
鈥?/div>
鈥?/div>
4.75
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0
鈥?0
500
15
鈥?/div>
Typ
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
150
(2)
5.5
2
鈥?/div>
(3)
Max
0.50
0.25
0.40
0.20
鈥?/div>
鈥?/div>
鈥?/div>
+V
o
鈥?
鹵3.0
鹵10
鹵1.0
鹵1.0
鹵3
鹵3
鈥?/div>
5
鈥?/div>
鈥?/div>
+85
(4)
+125
G鈥檚
G鈥檚
鈥?/div>
Units
A
A
%I
o
max
A
mSec
V
%V
o
%V
o
%V
o
%V
o
碌Sec
%V
o
%
kHz
擄C
擄C
鹵1.5
鹵5
鹵0.5
鹵0.5
鹵1.5
鹵2
100
3
85
650
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
6.5
grams
For technical support and more information, see inside back cover or visit www.ti.com

PT5062N 產(chǎn)品屬性

  • 12

  • 電源 - 板載

  • DC DC Converters

  • PT5060

  • 非隔離(POL)

  • 2

  • 4.75V

  • 14V

  • 15V

  • -15V

  • -

  • 400mA,200mA

  • 9W

  • -

  • -

  • 通孔

  • 12-SIP 模塊

  • -

  • 托盤

  • 0°C ~ 85°C

  • 85%

  • 9W

  • 296-20109PT5062N-ND

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