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PT5025N Datasheet

  • PT5025N

  • POSITIVE INPUT/NEGATIVE OUTPUT INTEGRATED SWITCHING REGULATO...

  • 140.58KB

  • 6頁

  • TI

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PT5020 Series
Positive Input/Negative Output
Integrated Switching Regulator
SLTS025B
(Revised 12/19/2001)
Features
鈥?/div>
Negative Output
鈥?/div>
Input Voltage Range:
+4.75 to +7 Volts
鈥?/div>
Laser-Trimmed
鈥?/div>
Small Footprint
鈥?/div>
Soft Start
鈥?/div>
5-Pin Mount Option
(Suffixes L & M)
Description
The PT5020 series of integrated
switching regulators (ISRs) convert a
positive input voltage, typically +5V, to a
negative output voltage for a wide range of
analog and datacom applications.
These Plus to Minus ISRs incorporate
a 鈥淏uck-Boost鈥?topology and are packaged
in the 3-pin, single in-line pin (SIP)
package configuration.
Pin-Out Information
Pin
Function
V
in
GND
V
out
Ordering Information
PT5021
o
= -3.3 Volts
PT5022
o
= -5 Volts
PT5023
o
= -9 Volts
PT5024
o
= -12 Volts
PT5025
o
= -15 Volts
PT5026
o
= -5.2 Volts
PT5027
o
= -8.0 Volts
PT5028
o
= -6.5 Volts
PT5029
o
= -5.5 Volts
PT5030
o
= -6.0 Volts
PT5031
o
= -1.7 Volts
PT Series Suffix
(PT1234x )
Case/Pin
Configuration
Vertical
Horizontal
SMD
Horizontal, 2-pin Tab
SMD, 2-Pin Tab
Order
Suffix
Package
Code *
(EAD)
(EAA)
(EAC)
(EAM)
(EAL)
Standard Application
+V
in
1
1
2
鈥揤
out
PT5020
2
3
3
C
1
C
2
100碌F +
N
A
C
M
L
COM
COM
* Previously known as package styles 100/110.
(Reference the applicable package code drawing
for the dimensions and PC board layout)
C
1
= Optional ceramic (1-5碌F)
C
2
= Required Electrolytic (100碌F)
NOTE: PT5020 ISRs are not Short-Circuit Protected.
Specifications
Characteristics
Output Current
(Unless otherwise stated, T
a
=25擄C, V
in
=5V, I
o
=I
o
max, C
2
=100碌F)
PT5020 SERIES
Symbol
I
o
Conditions
Over V
in
range
V
o
= 鈥?.7V to 鈥?.5V
V
o
= 鈥?V
V
o
= 鈥?2V
V
o
= 鈥?5V
Min
0.25
(1)
0.10
(1)
0.10
(1)
0.10
(1)
4.75
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
On start up
Over I
o
range
鈥?/div>
Free Air Convection
(40-60LFM)
Per Mil-STD-883D, Method 2002.3
1 msec, Half Sine, mounted to a fixture
Suffixes N, A, & C
Suffixes L & M
Suffixes N, A, & C
Suffixes L & M
錚
o
錚?/div>
=1.7 to 8V
錚
o
錚?鈮?
V
鈥?/div>
鈥?/div>
0.8
500
-20
鈥?/div>
-40
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Typ
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鹵1.5
鹵0.5
鹵0.5
75
鹵2
500
3.0
150
1.0
(3)
1.0
1
650
鈥?/div>
50
鈥?/div>
500
5
20
4.5
6.5
(5)
Max
1.0
0.60
0.50
0.30
7
(2)
鹵3
鹵1
鹵1
鈥?/div>
鹵5
鈥?/div>
5.0
鈥?/div>
鈥?/div>
鈥?/div>
1.2
800
+85
(4)
鈥?/div>
+125
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Units
A
V
%V
o
%V
o
%V
o
%
%V
o
碌Sec
%V
o
%I
o
max
A
mSec
MHz
kHz
擄C
擄C/W
擄C
G鈥檚
G鈥檚
grams
Input Voltage Range
Output Voltage Tolerance
Line Regulation
Load Regulation
Efficiency
V
o
Ripple (pk-pk)
Transient Response
Current Limit
Inrush Current
Switching Frequency
Operating Temperature Range
Thermal Resistance
Storage Temperature
Mechanical Shock
Mechanical Vibration
Per Mil-STD-883D, 20-2000 Hz
Weight
Notes:
(1)
(2)
(3)
(4)
(5)
V
in
鈭哣
o
Reg
line
Reg
load
畏
V
r
t
tr
I
lim
I
ir
t
ir
茠
s
T
a
Over I
o
range
Over V
in
Range
T
a
= -20擄C to SOA limit
(3)
Over V
in
range
I
o
min
鈮?/div>
I
o
鈮?/div>
I
o
max
I
o
=0.5 I
o
max
20MHz bandwidth
25% load change
V
o
over/undershoot
胃
ja
T
s
The ISR will operate at no load with reduced specifications.
For applications with input voltages greater than 7 VDC, use the PT78NR100 Series.
The inrush current stated is above the normal input current for the associated output load.
See Safe Operating Area curves or consult the factory for the appropriate derating
The tab pins on the 5-pin mount package types (suffixes L & M) must be soldered. For more information see the applicable package outline drawing.
For technical support and more information, see inside back cover or visit www.ti.com

PT5025N 產(chǎn)品屬性

  • 35

  • 電源 - 板載

  • DC DC Converters

  • PT5020

  • 非隔離（POL）

  • 1

  • 7V

  • -15V

  • -

  • -

  • 300mA

  • 4W

  • *

  • *

  • 通孔

  • 3-SIP 模塊

  • -

  • 托盤

  • -20°C ~ 85°C

  • 75%

  • 4.5W

  • 296-20086PT5025N-ND

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