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FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
DUAL BANK FLASH MEMORIES
鈥?4 Mbits of Primary Flash Memory (8
uniform sectors, 64Kbyte)
鈥?256 Kbits of Secondary Flash Memory
with 4 sectors
鈥?Concurrent operation: READ from one
memory while erasing and writing the
other
64 KBIT OF BATTERY-BACKED SRAM
52 RECONFIGURABLE I/O PORTS
ENHANCED JTAG SERIAL PORT
PLD WITH MACROCELLS
鈥?Over 3000 Gates of PLD: CPLD and
DPLD
鈥?CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
鈥?DPLD - user defined internal chip select
decoding
52 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
They can be used for the following functions:
鈥?MCU I/Os
鈥?PLD I/Os
鈥?Latched MCU address output
鈥?Special function I/Os.
鈥?I/O ports may be configured as open-drain
outputs.
IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
鈥?Built-in JTAG compliant serial port allows
full-chip In-System Programmability
鈥?Efficient manufacturing allow easy
product testing and programming
鈥?Use low cost FlashLINK cable with PC
PAGE REGISTER
鈥?Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
PROGRAMMABLE POWER MANAGEMENT
Figure 1. Package
TQFP80 (U)
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HIGH ENDURANCE:
鈥?100,000 Erase/WRITE Cycles of Flash
Memory
鈥?1,000 Erase/WRITE Cycles of PLD
鈥?15 Year Data Retention
5V鹵10% SINGLE SUPPLY VOLTAGE
STANDBY CURRENT AS LOW AS 50碌A
MEMORY SPEED
鈥?70ns Flash memory and SRAM access
time for V
CC
= 4.5V to 5.5V
鈥?90ns Flash memory and SRAM access
time for V
CC
= 4.5V to 5.5V
March 2004
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