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PSD813F1 Datasheet

  • PSD813F1

  • Flash In-System Programmable (ISP) Peripherals for 8-bit MCU...

  • 1681.85KB

  • 110頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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PSD813F1
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
FEATURES SUMMARY
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DUAL BANK FLASH MEMORIES
鈥?1 Mbit of Primary Flash Memory (8
Uniform Sectors)
鈥?256 Kbit Secondary EEPROM (4 Uniform
Sectors)
鈥?Concurrent operation: read from one
memory while erasing and writing the
other
16 Kbit SRAM (BATTERY-BACKED)
PLD WITH MACROCELLS
鈥?Over 3,000 Gates Of PLD: DPLD and
CPLD
鈥?DPLD - User-defined Internal chip-select
decoding
鈥?CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
27 RECONFIGURABLE I/Os
鈥?27 individually configurable I/O port pins
that can be used for the following
functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note:
16 of the I/O ports may be
configured as open-drain outputs.
ENHANCED JTAG SERIAL PORT
鈥?Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
鈥?Efficient manufacturing allows for easy
product testing and programming
PAGE REGISTER
鈥?Internal page register that can be used to
expand the microcontroller address space
by a factor of 256.
PROGRAMMABLE POWER MANAGEMENT
Figure 1. Packages
PQFP52 (M)
PLCC52 (J)
TQFQ64 (U)
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HIGH ENDURANCE:
鈥?100,000 Erase/WRITE Cycles of Flash
Memory
鈥?10,000 Erase/WRITE Cycles of EEPROM
鈥?1,000 Erase/WRITE Cycles of PLD
鈥?Data Retention: 15-year minimum at 90擄C
(for Main Flash, Boot, PLD and
Configuration bits).
SINGLE SUPPLY VOLTAGE:
鈥?5V鹵10% for 5V
STANDBY CURRENT AS LOW AS 50碌A(chǔ)
August 2004
1/110

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