鈥?/div>
Digitally programmable in 7 steps
Monotonic pulse-width-vs-address variation
Rising edge triggered
Two separate outputs: inverting & non-inverting
Precise and stable pulse width
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
Fits standard 14-pin DIP socket
Auto-insertable
data
3
廬
delay
devices,
inc.
PACKAGES
TRIG
TRIG
OUT
N/C
N/C
N/C
RES
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
OUT/
N/C
N/C
A0
A1
A2
OUT
N/C
N/C
N/C
N/C
RES
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
OUT/
N/C
N/C
N/C
A0
A1
A2
DIP
PPG33F-xx Commercial
PPG33F-xxM Military
Gull-Wing
PPG33F-xxC3 Commercial
PPG33F-xxMC3 Military
FUNCTIONAL DESCRIPTION
The PPG33F-series device is a 3-bit digitally programmable pulse
generator. The width, PW
A
, depends on the address code (A2-A0)
according to the following formula:
PW
A
= PW
0
+ T
INC
* A
PIN DESCRIPTIONS
TRIG
OUT
OUT/
A0-A2
RES
VCC
GND
Trigger Input
Non-inverted Output
Inverted Output
Address Bits
Reset
+5 Volts
Ground
where A is the address code, T
INC
is the incremental pulse width of the
device, and PW
0
is the inherent pulse width of the device. The
incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns,
inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are
forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The
address is not latched and must remain asserted while the output pulse is active.
SERIES SPECIFICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Programmed pulse width tolerance:
5% or 1ns,
whichever is greater
Inherent width (PW
0
):
9ns typical
Inherent delay (T
TO
):
3.5ns
鹵
2ns
Operating temperature:
0擄 to 70擄 C
Supply voltage V
CC
:
5VDC
鹵
5%
Supply current:
I
CC
= 41ma typical
DASH NUMBER SPECIFICATIONS
Part
Number
PPG33F-.5
PPG33F-1
PPG33F-2
PPG33F-3
PPG33F-4
PPG33F-5
PPG33F-6
PPG33F-8
PPG33F-10
PPG33F-20
PPG33F-30
PPG33F-40
PPG33F-50
Incremental Width
Per Step (ns)
0.5
鹵
0.3
1
鹵
0.4
2
鹵
0.4
3
鹵
0.5
4
鹵
0.5
5
鹵
0.6
6
鹵
0.7
8
鹵
0.8
10
鹵
1.0
20
鹵
1.5
30
鹵
1.8
40
鹵
2.0
50
鹵
2.5
Total Width
Change (ns)
3.50
鹵
1.00
7.00
鹵
1.00
14.0
鹵
1.00
21.0
鹵
1.05
28.0
鹵
1.40
35.0
鹵
1.75
42.0
鹵
2.10
56.0
鹵
2.80
70.0
鹵
3.50
140
鹵
7.00
210
鹵
10.5
280
鹵
14.0
350
鹵
17.5
漏
1997 Data Delay Devices
NOTE: Any dash number between .5 and 50 not
shown is also available.
Doc #97010
1/15/97
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PPG33F-10相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
Programmable 3-bit TTL pulse generator
ETC
-
英文版
3-BIT PROGRAMMABLE
PULSE GENERATOR
DATA DELAY DEVI...
-
英文版
Programmable 6-bit TTL pulse generator
ETC
-
英文版
6-BIT PROGRAMMABLE
PULSE GENERATOR
DATA DELAY DEVI...
-
英文版
Programmable 8-bit TTL pulse generator
ETC
-
英文版
8-BIT PROGRAMMABLE
PULSE GENERATOR
DATA DELAY DEVI...
-
英文版
12-BIT PROGRAMMABLE PULSE GENERATOR(SERIES PPG312F)
ETC
-
英文版
12-BIT PROGRAMMABLE
PULSE GENERATOR
DATA DELAY DEVI...
-
英文版
12-BIT PROGRAMMABLE PULSE GENERATOR(SERIES PPG312F)
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
-
英文版
Logic IC
ETC
1
2
3
4
5
