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PPC403GA-JC33C1 Datasheet

  • PPC403GA-JC33C1

  • 32-Bit Microprocessor

  • 44頁

  • ETC

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PowerPC 403GA
32-Bit RISC
Embedded Controller
Features
鈥?/div>
PowerPC
鈩?/div>
RISC CPU and instruction set
architecture
鈥?/div>
Glueless interfaces to DRAM, SRAM,
ROM, and peripherals, including byte and
half-word devices
鈥?/div>
Separate instruction cache and write-back
data cache, both two-way set-associative
鈥?/div>
Minimized interrupt latency
鈥?/div>
Individually programmable on-chip
controllers for:
鈥揊our DMA channels
鈥揇RAM, SRAM, and ROM banks
鈥揚eripherals
鈥揝erial port
鈥揈xternal interrupts
鈥?/div>
Flexible interface to external bus masters
Data
Sheet
Overview
The PowerPC 403GA 32-bit RISC embedded
controller offers high performance and functional
integration with low power consumption. The
403GA RISC CPU executes at sustained speeds
approaching one cycle per instruction. On-chip
caches and integrated DRAM and SRAM control
functions reduce chip count and design
complexity in systems, while improving system
throughput.
External I/O devices or SRAM/DRAM memory
banks can be directly attached to the 403GA bus
interface unit (BIU). Interfaces for up to eight
memory banks and I/O devices, including a
maximum of four DRAM banks, can be
configured individually, allowing the BIU to
manage devices or memory banks with differing
control, timing, or bus width requirements.
Interrupt
Controller
JTAG
Port
Serial
Port
4-Channel
DMA
Controller
(Address
and
Control)
鈥?/div>
Hardware multiplier and divider for faster
integer arithmetic
鈥?/div>
Thirty-two 32-bit general purpose registers
Applications
鈥?/div>
Set-top boxes
鈥?/div>
Consumer electronics and video games
鈥?/div>
Telecommunications and networking
鈥?/div>
Office automation (printers, copiers, fax
machines)
鈥?/div>
Personal digital assistants (PDA)
Specifications
鈥?/div>
25MHz, and 33MHz, and 40MHz versions
鈥?/div>
Interfaces to both 3V and 5V technologies
鈥?/div>
Low-power 3.3V operation with built-in
power management and stand-by mode
鈥?/div>
Low-cost 160 lead PQFP package
鈥?/div>
0.5
碌
m triple-level-metal CMOS
Timers
RISC Execution Unit
Instruction
Data
Cache Unit Cache Unit
On-chip
Peripheral
Bus
Bus Interface Unit
DRAM Controller
I/O Controller
Data Address
Bus Bus
DRAM
Controls
SRAM, ROM, I/O
Controls

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