used with SONET/SDH mapper.
鈥?/div>
Supports insertion and extraction of
arbitrary rate (eg. fractional DS3)
data streams to/from the SBI bus
interface.
鈥?Provides jitter attenuation in the T1/E1
tributary receive and transmit
directions.
鈥?Provides three independent de-jittered
T1 or E1 recovered clocks for system
timing and redundancy.
鈥?Provides per link diagnostic and line
loopbacks.
鈥?Provides PRBS generators and
detectors at DS3 and E3 rates and on
each tributary for error testing at T1,
E1 and NxDS0 rates as recommended
in ITU-T O.151, 0.152.
鈥?Feature-rich functional software drivers
available with device.
鈥?Provides a generic 8-bit
microprocessor bus interface for
configuration, control and status
monitoring.
鈥?Provides a standard 5 signal P1149.1
JTAG test port for boundary scan
board test purposes.
VOLTAGE
鈥?Low power 1.8 V/3.3 V CMOS
technology. All pins are 5 V tolerant.
PACKAGE
鈥?324-pin fine pitch PBGA package
(23 mm x 23 mm).
鈥?Supports industrial temperature range
(-40
o
C to 85
o
C) operation.
BLOCK DIAGRAM
Telecom
Bus
19.44/77.76 MHz
Mapper
and
Telecom
Bus I/F
M13
M13
Multiplex
Multiplex
er
M13 Mux
er
DS3
DS3
Framer
Framer
DS3/E3
with
with
Framer
PRBS
PRBS
with
PRBS
T1/E1
Framer
RJAT
84xT1/63xE1
on 21 H-MVIP buses
PRBS
Scaleable Bandwidth
Interconnect Bus
19.44/77.76 MHz
PMON
T1/E1
Transmitter
3xDS3
TJAT
DS3
Clock and Data
PMC-2001514 (p2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2001
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