PMC-Sierra,Inc.
PM7384
FREEDM-84P672
Frame Engine and Data Link Manager
FEATURES
鈥?Single-chip multi-channel HDLC
controller with a 66 MHz, 32 bit PCI 2.1
compatible bus for configuration,
monitoring and transfer of packet data.
鈥?On-chip DMA controller with scatter/
gather capabilities.
鈥?Supports up to 672 bi-directional
HDLC channels assigned to a
maximum of 84 channelised or
unchannelised links conveyed via a
19.44 MHz Scalable Bandwidth
Interconnect (SBI鈩? interface.
鈥?Data on the SBI interface is divided
into three Synchronous Payload
Envelopes (SPEs). Each SPE can be
configured independently to carry data
for either 28 T1/J1 links, 21 E1 links, or
one unchannelised DS-3 link.
鈥?Supports three bi-directional HDLC
channels each assigned to an
unchannelised link with arbitrary rate
link of up to 51.84 MHz when SYSCLK
is running at 45 MHz. Each link may be
configured individually to replace one
of the SPEs conveyed on the SBI
interface.
鈥?For each channel, the HDLC receiver
supports programmable flag sequence
detection, bit de-stuffing and frame
check sequence validation. The
receiver supports the validation of both
CRC-CCITT and CRC-32 frame check
sequences.
鈥?For each channel, the HDLC
transmitter supports programmable
flag sequence generation, bit stuffing
and frame check sequence generation.
The transmitter supports the
generation of both CRC-CCITT and
CRC-32 frame check sequences. The
transmitter also aborts packets under
the direction of the host or
automatically when the channel
underflows.
鈥?Provides 32 Kbytes of on-chip memory
for partial packet buffering in both the
transmit and receive directions. This
memory may be configured to support
a variety of different channel
configurations from a single channel
with 32 Kbytes of buffering to 672
channels, each with a minimum of 48
bytes of buffering.
鈥?Provides a standard five signal
P1149.1 JTAG test port for boundary
scan board test purposes.
鈥?Supports 3.3 Volt I/O on non-PCI
signals. Supports 3.3 Volt PCI
signaling environment.
鈥?352 pin enhanced ball grid array
(SBGA) package.
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PPP interfaces for routers.
Internet/Edge Routers.
Frame Relay/Multiservice Switches.
Packet-based DSLAM equipment.
Remote Access Concentrators.
Multiservice Access Concentrators.
BLOCK DIAGRAM
PMCTEST
C1FPOUT
C1FP
FASTCLK
REFCLK
SPE3_EN
SPE2_EN
SPE1_EN
SYSCLK
RSTB
RCLK[2:0]
RD[2:0]
AD[31:0]
C/BEB[3:0]
PAR
FRAMEB
TRDYB
IRDYB
STOPB
DEVSELB
IDSEL
LOCKB
REQB
GNTB
PERRB
SERRB
PCIINTB
PCICLK
PCICLKO
M66EN
DDATA[7:0]
DPL
DV5
DDP
SBI
Extract
Receive
Channel
Assigner
(RCAS672)
Receive
HDLC Processor
(RHDL672)
Receive
DMA
Controller
(RMAC672)
Performance
Monitor
(PMON)
ADATA[7:0]
APL
AV5
ADP
AJUST_REQ
AACTIVE
ADETECT[1:0]
TD [2:0]
TCLK[2:0]
Transmit
Channel
Assigner
(TCAS672)
Transmit
DMA
Controller
(TMAC672)
PCI
Controller
(GPIC672)
SBI
Insert
Transmit
HDLC Processor
(THDL672)
JTAG
TRSTB
TMS
TCK
TD1
PMC-1991024 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
TD0
漏 2001 PMC-Sierra, Inc.
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