Release
PM7328
S/UNI-ATLAS-1K800
ATM Layer Solution
FEATURES
鈥?Monolithic single chip device which
handles bi-directional ATM Layer
functions including VPI/VCI address
translation, cell appending, policing
(ingress only), cell counting and OAM
requirements for 1024 VCs (virtual
connections).
鈥?Instantaneous bi-directional transfer
rate of 800 Mbit/s supports a bi-
directional cell transfer rate of
1.42x10
6
cell/s.
鈥?Ingress input interface supports an 8 or
16 bit PHY interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
鈥?Ingress output interface supports an 8
or 16 bit SCI-PHY (52 - 64 byte cell)
interface (Utopia Level 1) to a switch
fabric.
鈥?Egress input and output interfaces
support an 8 or 16 bit SCI-PHY (52 -
64 byte cell) interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
鈥?Compatible with the PM7329 S/UNI-
APEX-1K800 Traffic Manager, and
PMC-Sierra鈥檚 VORTEX Architecture.
鈥?Ingress functionality includes a highly
flexible search engine that covers the
entire PHYID/VPI/VCI address range,
dual leaky bucket policing, per-VC cell
counts, OAM-FM and OAM-PM
processing.
鈥?Egress functionality includes direct
address lookup, per-VC cell counts,
OAM-FM and OAM-PM processing.
Per-PHY output buffering scheme
resolves the head-of-line blocking
issue.
鈥?Includes a FIFO buffered 16-bit
microprocessor bus interface for cell
insertion and extraction, deterministic
VC Table access, status monitoring
and configuration of the device.
鈥?Supports DMA access for cell
extraction.
鈥?The UTOPIA and external SRAM
interfaces are 52 MHz max.
POLICING
鈥?ITU-I.371, ATM Forum TM4.0
compliant, per-VC programmable dual
leaky bucket policing with a
programmable action (tag, discard, or
count only) for each bucket, each with
3 programmable 16 bit non-compliant
cell counts.
鈥?Per-PHY single leaky bucket policing
with a programmable action (tag,
discard, or count only).
SCI-PHY Level 1/ Level 2
Interface (Master)
RDAT[15:0]
RPRTY
RDRENB[1]
RCA[1]
RADDR[4:3]/RCA[3:2]
RAVALID/RCA[4]
RADDR[2:0]/RRDENB[4:2]
RSOC
RFCLK
RPOLL
ISYSCLK
ISD[63:0]
ISP[7:0]
ISA[19:16]
ISA[9:0]
ISWRB
ISOEB
ISADSB
BLOCK DIAGRAM
To External Synchronous SRAM
SCI-PHY Level 1
Interface (Slave)
ODAT[15:0]
OPRTY
OSOC
OFCLK
OCA
ORDENB
OTSEN
Ingress
Input Cell
Interface
Ingress
Search
Engine
Ingress
Cell
Processor
Ingress
Output Cell
Interface
Ingress
Backward
Cell
Interface
PHY
Statistics
Collection
Egress
Backward
Cell
Interface
Egress
Input Cell
Interface
IDAT[15:0]
IPRTY
IFCLK
ISOC
ICA[1]
IWRENB[1]
IAVALID/ICA[4]
IADDR[4:3]/ICA[3:2]
IADDR[2:0]/IWRENB[4:2]
IPOLL
TDAT[15:0]
TPRTY
TWRENB[1]
TCA[1]
TADDR[4:3]/TCA[3:2]
TAVALID/TCA[4]
TADDR[2:0]/TDWRENB[4:2]
TSOC
TFCLK
TPOLL
Egress
Output Cell
Egress
Cell
Processor
Ingress
Microprocessor Cell
Interface
Egress
Microprocessor Cell
Interface
JTAG
Interface
Microprocessor Interface
ESD[31:0]
ESP[3:0]
ESA[19:16]
ESA[9:0]
ESADSB
ESRWB
ESOEB
ESYSCLK
SCI-PHY Level 1/ Level
2 Interface (Master)
SCI-PHY Level 1/ Level
2 Interface (Slave)
To External Synchronous SRAM
PMC-2010037 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2001
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