PM6341
Summary Information
E1 TRANSCEIVER
FEATURES
鈥?Monolithic single chip device which
integrates a full-featured E1 framer
with on-chip analog line interface.
鈥?Provides frame synchronization and
frame generation for a G.704/G.706
2.048 Mbit/s signal with capability to
support the optional signalling and
CRC multiframes.
鈥?Supports HDB3 or AMI line coding
and accepts gapped data streams to
support higher rate demultiplexing.
鈥?Supports both 75 Ohm and 120 Ohm
G.703 line interfaces.
鈥?Provides Channel Associated
Signalling extraction/insertion,
programmable idle code substitution,
digital milliwatt code substitution,
data inversion and up to 3
multiframes of signalling debounce
on a per channel basis.
鈥?Optionally extracts/inserts the
datalink from/to timeslot 16 to
receive/transmit Common Channel
Signalling.
鈥?Pin compatible with the PM4341A
T1XC T1 Transceiver.
鈥?Software compatible with the
PM6344 EQUAD E1 Framer, and
PM6388 EOCTL E1 Framer.
鈥?Provides an 8-bit microprocessor bus
interface for configuration, control
and status monitoring.
鈥?Low-power 5V CMOS technology.
鈥?Available in a high density 80-pin (14
by 14mm) PQFP or in a 68-pin PLCC
package.
A(7-0)
R DB
WRB
C SB
ALE
INTB
R STB
M P IF
MIC RO-
PRO CESSOR
INTERFAC E
E
1XC
RECEIVE SECTION
鈥?Provides indications of loss of
signal, loss of frame alignment
(OOF), loss of signalling multiframe
alignment and loss of CRC
multiframe alignment.
鈥?Declares red and AIS alarms using
Q.516 recommended integration
periods
鈥?Supports line and path performance
monitoring according to ITU-T
recommendations. Accumulators
are provided for CRC-4 errors, Far
End Block Errors, Frame sync errors,
and Line Code Violations.
鈥?Provides an integral HDLC/LAPD
interface which may be used for
terminating a CCS or National Bits
datalink.
鈥?Provides a two frame elastic store for
jitter and wander attenuation.
鈥?Provides programmable trunk
conditioning on a per channel basis.
TRANSMIT SECTION
鈥?Supports transmission of AIS,
timeslot 16 AIS, remote alarm signal
or remote multiframe alarm signal.
鈥?Provides an integral HDLC/LAPD
interface which may be used for
generating a CCS or National Bits
datalink.
鈥?Provides an integrated digital phase
locked loop for generation of a low
jitter transmit clock.
鈥?Provides a FIFO buffer for jitter
attenuation and rate conversion.
鈥?Provides programmable trunk
conditioning which forces trouble
code substitution and signalling
conditioning on a per channel basis.
BLOCK DIAGRAM
TCLKI
B TIF
BAC K-
PLANE
TRANS-
MIT
INTER-
FAC E
TRA N
TRANSMITTER:
FRAME GENERATIO N,
ALARM IN SER TIO N,
TRU NK CON D ITION ING
LIN E C OD IN G
TOPS
TIM ING OPTIO NS
TR A N S M ITT E R
XPLS
ANALO G
PULSE
GEN ER ATOR
BTPCM /BTDP
BTSIG/BTD N
BTFP
BTC LK
TAP
D JA T
D IGITAL JITTER
ATTEN UATOR
TAN
INTERN AL
BUS
PCSC
PER -C H AN
C ON TR :
SIG NAL,
IDLE C ON T
XBOC
BIT-
OR IEN TED
C OD E
TRANS
X FD L
TC
D TIF
D IGITAL
TRANSMIT
INTERFAC E
TCLKO
TDP/TD D
TDN /TFLG
TDLCLK/
TDLUD R
TDLSIG/
TDLINT
H DLC
TRANS-
MITTER
APPLICATIONS
鈥?E1 & E3 Multiplexers
鈥?Digital Loop Carriers
鈥?E1 Frame Relay Interfaces
D (7-0)
BRC LK
鈥?E1 ATM UNI Interfaces
鈥?E1 Channel Service Units (CSUs)
and Data Service Units (DSUs)
鈥?Digital Access and Cross-Connect
Systems (DACS) and Electronic
Digital Cross-Connect Systems
(EDSX)
鈥?SDH Add/Drop Multiplexers (ADM)
鈥?ISDN Primary Rate Interfaces (PRI)
鈥?Digital Private Branch Exchanges
(PBX)
鈥?E1 & E3 Test Equipment
PMC-920109(R6)
BRFPI
XCLK/VCLK
R AS
R EF
R RC
R SLC
PMON
R E C E IV E R
S IG X
SIG NALLIN G
EXTRACT,
TRU NK
C ON DITION
ANALO G
PULSE
SLIC ER
PER F
MONITOR
C OU NTER S
E LS T
BRPCM /BR DP
B R IF
ELASTIC
STO RE
BRSIG/BR DN
BRFPO
R CLKI
R DP/R DD /
SDP
R DN /RLCV/
SDN
D R IF
D IGITAL
R EC EIVE
INTERFAC E
C DR C
C LO CK AN D
D ATA
R EC OVER Y
FRM R
FR AMER:
FRAME
ALIG NM EN T,
ALARM
D ETEC TIO N
R B OC
BAC K-
PLANE
R EC EIVE
INTER-
FAC E
R DPCM/RPCM
R CLKO
R FP
BIT
OR IEN TED
C OD E
D ETEC TOR
R FD L
R DLSIG/
R DLINT
R DLCLK/
R DLEOM
H DLC
R EC EIVER
漏 1998 PMC-Sierra, Inc. March, 1998
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