Advance
PM5384
S/UNI廬-1x155
Single Channel OC-3c ATM and POS Physical Layer Device
FEATURES
鈥?Single chip ATM and Packet over
SONET/SDH Physical Layer Device
operating at 155.52 Mbit/s.
鈥?Implements the ATM Forum User
Network Interface (UNI) and the ATM
physical layer for Broadband ISDN
according to CCITT Recommendation
I.432.
鈥?Implements Point-to-Point Protocol
(PPP) over SONET/SDH according to
RFC 2615.
鈥?Processes duplex bit-serial 155.52
Mbit/s STS-3c/STM-1 data streams
with on-chip clock and data recovery
and clock synthesis.
鈥?Complies with Bellcore GR-253-CORE
(1995 Issue) jitter tolerance, jitter
transfer and intrinsic jitter criteria.
鈥?Provides control circuitry required to
comply with Bellcore GR-253-CORE
WAN clocking requirements related to
wander transfer, holdover and long
term stability when using an external
VCXO.
鈥?Provides a UTOPIA Level 2, 8-bit wide
system interface (clocked up to 52
MHz) with parity support for ATM
applications.
鈥?Provides a UTOPIA Level 2, 16-bit
wide system interface (clocked up to
52 MHz) with parity support for ATM
applications.
鈥?Provides a SATURN POS-PHY Level
2, 16-bit system interface (clocked up
to 52 MHz) for Packet over
SONET/SDH (POS) applications
(similar to UTOPIA Level 2, but
adapted for packet transfer).
鈥?Provides support functions for 1+1
APS operation.
鈥?Low power 2.5/3.3 V CMOS with 5 V
TTL-compatible digital inputs/outputs
(PECL inputs/outputs are 3.3 V and
5 V compatible).
鈥?Industrial temperature range (-40擄C to
+85擄C).
鈥?15 mm x15 mm 196 pin stPBGA
package with 1 mm ball pitch.
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Routers and Layer 3 Switches.
3G Wireless Base Station Controllers.
DSLAM Uplinks.
WAN and Edge ATM switches.
LAN switches and hubs.
Packet switches and hubs.
Network Interface Cards and Uplinks.
GENERAL
鈥?Provides a standard 5 signal IEEE
1149.1 JTAG test port for boundary
scan board test purposes.
鈥?Provides a generic 8-bit
microprocessor bus interface for
configuration, control and status
monitoring.
BLOCK DIAGRAM
Section/
Line DCC
Insertion
Tx
POS Frame
Processor
Tx
Line O/H
Processor
Tx
Path O/H
Processor
Tx
Section O/H
Processor
UTOPIA Level 2/POS-PHY Level 2
System Interface
Serial Line Interface
Path Crossbar/
APS Crossconnect
Tx
ATM Cell
Processor
155.52 Mbit/s
Section
Trace Buffer
WAN
Synch.
Path
Trace Buffer
Rx
ATM Cell
Processor
Rx
Path O/H
Processor
Rx
POS Frame
Processor
UTOPIA Level 1
8-bit x 52 MHz
UTOPIA Level 2
POS-PHY Level 2
16-bit x 52 MHz
Rx
Section O/H
Processor
Rx
Line O/H
Processor
Section/
Line DCC
Extraction
Sync Status,
BERM
JTAG Test
Access Port
External
APS
Interface
Microprocessor Interface
Test Data
16-bit
Microprocessor
Bus
APSO +/-
APSI +/-
APECLV
PMC-2011690 (A1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2001.
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