Advance
PM5358
S/UNI廬-4x622
Quad Channel OC-12c ATM and POS Physical Layer Device
FEATURES
鈥?Single chip quad ATM and POS User-
Network Interface operating at
622 Mbit/s.
鈥?Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT
Recommendation I.432.
鈥?Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
鈥?Processes four bit-serial 622 Mbit/s
STS-12c (STM-4-4c) data streams
with on-chip clock and data recovery
and clock synthesis.
鈥?Complies with Bellcore GR-253-CORE
jitter tolerance, jitter transfer and
intrinsic jitter criteria.
鈥?Each channel provides termination for
SONET Section, Line and Path
overhead or SDH Regenerator
鈥?/div>
Section, Multiplexer Section and High
Order Path overhead.
Provides UTOPIA Level 3 32-bit wide
System Interface (clocked up to
104 MHz) with parity support for ATM
applications.
Provides SATURN POS-PHY
Level 3鈩?32-bit System Interface
(clocked up to 104 MHz) for Packet
over SONET (POS), or ATM
applications.
Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
the line side transmit stream to the line
side receive stream interface.
Provides support for automatic
protection switching including a bi-
directional 4-bit PECL 622 MHz port
for external APS with mate device.
Built-in APS cross-connect for internal
and external 1+1 and 1:n protection
switching.
Provides a standard five signal IEEE
1149.1 JTAG test port for boundary
鈥?/div>
scan board test purposes.
Provides a generic 16-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
Low power 2.5 V CMOS core logic with
3.3 V CMOS/TTL compatible digital
inputs and digital outputs. PECL inputs
and outputs are 3.3 V compatible.
Industrial temperature range (-40擄 C to
+85擄 C).
520 pin SBGA package.
Pin and software compatible with
PM5382 S/UNI-16x155.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
APPLICATIONS
鈥?ATM and Multiservice Switches,
Routers, and Switch/Routers.
鈥?SONET/SDH Add/Drop Multiplexers
with data processing capabilities
鈥?Uplink Cards.
鈥?SONET/SDH ATM/POS Test
Equipment.
鈥?/div>
鈥?/div>
BLOCK DIAGRAM
TDCLK[3:0]
TACLK[3:0]
TDCC[3:0]
TACC[3:0]
TFPO
TCLK
TFPI
Section/
Line DCC
Insertion
Tx
Section O/H
Processor
Tx
Line O/H
Processor
Tx
Path O/H
Processor
TFCLK
Tx
POS Frame
Processor
TENB
TADR[3:0]
TSX
Serial Line Interface
TXD[3:0]+/-
RXD[3:0]+/-
SD[3:0]
REFCLK+/-
C1[3:0], C0[3:0]
TDREF1, TDREF0
ATP[1:0]
QAVD[2:0]
QAVS[2:0]
AVD[45:0]
AVS[45:0]
SPECLV
SDTTL
Path Crossbar/
APS Crossconnect
Tx
ATM Cell
Processor
Path
Trace Buffer
Rx
ATM Cell
Processor
UTOPIA Level 3/POS-PHY Level 3
System Interface
TCA/TPA
STPA
TSOC/TSOP
TPRTY
TDAT[31:0]
TMOD[1:0]
TEOP
TERR
RFCLK
RENB
RADR[3:0]
RSX
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[31:0]
RMOD[1:0]
REOP
RERR
Section
Trace Buffer
WAN
Synch.
Rx
Section O/H
Processor
Rx
Line O/H
Processor
Rx
Path O/H
Processor
Rx
POS Frame
Processor
Section/
Line DCC
Extraction
Sync Status,
BERM
JTAG
External
APS
Interface
Microprocessor
Interface
RFPO
RCLK
APREF0, APREF1
RALRM[3:0]
RACC[3:0]
RDCC[3:0]
TRSTB
RSTB
TDI
TCK
ALE
CSB
RACLK[3:0]
RDCLK[3:0]
APECLV
APSO[3:0]+/-
APSI[3:0]+/-
INTB
A [11:0]
WDB
RDB
TMS
TDO
D [15:0]
PMC-2000331 (A2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2000
POS_ATMB
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