PMC-Sierra,Inc.
PM5342
SPECTRA鈩?155
鈥?Maps three DS3 bit streams into a
STS-3 (STM-1/AU3) frame.
鈥?Maps three serial data streams (e.g.,
Frame Relay, PPP, or Ethernet
Payload) into a single serial data
stream into a STS-1 (STM-0/AU3) or
STS-3c (STM-1/AU4) payload.
鈥?Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from a
Telecom ADD bus interface to a
Telecom DROP bus interface.
鈥?Provides a standard 5-signal P1149.1
JTAG test port for boundary scan
board test purposes.
鈥?Provides a generic 8-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
鈥?Low power, +5 V, CMOS technology.
Device has PECL- and TTL-
compatible inputs and TTL outputs.
鈥?Available in a 256-pin, Super Ball Grid
Array (SBGA) package.
鈥?Supports industrial temperature range
(-40擄C to 85擄C) operation.
SONET/SDH Payload Extractor/Aligner
FEATURES
鈥?Monolithic, SONET/SDH Payload
Extractor/Aligner for use in STS-1
(STM-0/AU3), STS-3 (STM-1/AU3) or
STS-3c (STM-1/AU4) interface
applications, operating at serial interface
speeds up to 155.52 Mbit/s.
鈥?Provides integrated clock recovery and
clock synthesis to allow a direct interface
to optical modules.
鈥?Provides termination for SONET Section
and Line, SDH Regenerator Section and
Multiplexer Section transport overhead,
and Path overhead of one or three
STS-1 (STM-0/AU3) paths or a single
STS-3c (STM-1/AU4) path.
鈥?Maps one or three STS-1 (STM-0/AU3)
payloads or a single STS-3c (STM-1/
AU4) payload to system timing
reference, accommodating
plesiochronous timing offsets between
the references through pointer
processing.
TSLDCLK, TOWCLK
TSLD, TSOW, TSUC
BACKPLANE/DEVICE MODES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Telecom Byte.
Telecom Nibble.
Telecom Serial.
Datacom Byte.
Datacom Nibble.
Datacom Serial.
Datacom T3.
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
SONET/SDH Add/Drop Multiplexers
SONET/SDH Terminal Multiplexers
SONET/SDH Digital Cross-Connects
Channelized Routers and Switches
Packet Over SONET Router and
Switches
TLDCLK, TOHCLK
BLOCK DIAGRAM
RLAIS/TRCPCLK
TLRDI/TRCPFP
TLAIS/TRCPDAT
TAD, TAFP, TACK
TLD, TLOW, TOH
TPOHCLK[3:1]
TPOHEN[3:1]
TPOHFP[3:1]
TCLK, TFP
TPOH[3:1]
TTOH
TTOHFP
TTOHCLK
TTOHEN
SCPO[1:0]
SCPI[1:0]
TDO
TDI
TCLK
TMS
TRSTB
Transmit Ring
Control Port
Transmit
O/H
Insert
Serial
Control
Port
JTAG
Test Access
Port
3
3
Add Bus PRBS
Generator/
Monitor
DS3 Mapper
Add Side #1
DS3 Mapper
Add Side #2
DS3 Mapper
Add Side #3
TRCLK+
TRCLK-
TXC
TXD+
TXD-
TBYP
TATP
Section
Trace
Buffer
RATP
RBYP
RXD+
RXD-
RRCLK+
RRCLK-
ALOS+
ALOS-
Receive
Line
Interface
Transmit
Line
Interface
Transmit
Section O/H
Processor
Transmit
Line O/H
Processor
Transmit Path O/H
Processor #1
Transmit Path O/H
Processor #2
Transmit Path O/H
Processor #3
Path
Trace
Buffer
#1
Path
Trace
Buffer
#2
Path
Trace
Buffer
#3
Receive Telecom
Aligner #1
Receive Telecom
Aligner #2
Receive Telecom
Aligner #3
Transmit Telecom
Aligner #1
Transmit Telecom
Aligner #2
Transmit Telecom
Aligner #3
3
Clock
Synthesis
System Side Interface
3
Clock &
Data
Recovery
Receive
Section O/H
Processor
Receive
Line O/H
Processor
Receive Path O/H
Processor #1
Receive Path O/H
Processor #2
Receive Path O/H
Processor #3
Transmit
Pointer
Interpreter #1
Transmit
Pointer
Interpreter #2
Transmit
Pointer
Interpreter #3
SMODE[2:0]
SS[34:0]
3
Drop Bus PRBS
Generator/
Monitor
DS3 Mapper
Drop Side #1
3
Microprocessor
Interface
DS3 Mapper
Drop Side #2
DS3 Mapper
Drop Side #3
3
Receive Ring
Control Port
Transmit
O/H
Extract
RTOHFP
RSLDCLK, ROWCLK
RXC, RCLK, RFP
RPOH[3:1]
C1, C2
LOS/RRCPFP
LRDI/RRCPCLK
LAIS/RRCPDAT
RTOHCLK
RTOH
RALM[3:1]
RTCEN[3:1]
RPOHCLK[3:1]
RPOHFP[3:1]
RSLD, RSOW, RSUC
RTCOH[3:1]
LOF, SALM
TRIS_OHB
B3E[3:1]
RAD
RLDCLK, ROHCLK
RLD, RLOW, ROH
ALE
CSB
WRB/RWB
RDB/E
RSTB
INTB
MBEB
D [7:0]
A [7:0]
PMC-1970791 (R3)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
錚?/div>
Copyright PMC-Sierra, Inc. 2001
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