Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
脳
64
脳
8)
PLUS405-55
DESCRIPTION
The PLUS405-55 device is a bipolar,
programmable state machine of the Mealy
type. Both the AND and the OR array are
user-programmable. All 64 AND gates are
connected to the 16 external dedicated inputs
(I0 - I15) and to the feedback paths of the
8 on-chip State Registers (Q
P0
- Q
P7
). Two
complement arrays support complex
IF-THEN-ELSE state transitions with a single
product term (input variables C
0
, C
1).
All state transition terms can include True,
False and Don鈥檛 Care states of the controlling
state variables. All AND gates are merged
into the programmable OR array to issue the
next-state and next-output commands to their
respective registers. Because the OR array is
programmable, any one or all of the 64
transition terms can be connected to any or
all of the State and Output Registers.
All state (Q
P0
- Q
P7
) and output (Q
F0
- Q
F7
)
registers are edge-triggered, clocked J-K
flip-flops, with Asynchronous Preset and
Reset options. The PLUS405 architecture
provides the added flexibility of the J-K toggle
function which is indeterminate on S-R
flip-flops. Each register may be individually
programmed such that a specific
Preset-Reset pattern is initialized when the
initialization pin is raised to a logic level 鈥?鈥?
This feature allows the state machine to be
asynchronously initialized to known internal
state and output conditions prior to
proceeding through a sequence of state
transitions. Upon power-up, all registers are
unconditionally preset to 鈥?鈥? If desired, the
initialization input pin (INIT) can be converted
to an Output Enable (OE) function as an
additional user-programmable feature.
Availability of two user-programmable clocks
allows the user to design two independently
clocked state machine functions consisting of
four state and four output bits each.
Order codes are listed in the Ordering
Information Table below.
FEATURES
鈥?/div>
66.7MHz minimum guaranteed clock rate
鈥?/div>
55MHz minimum guaranteed operating
鈥?/div>
Functional superset of PLS105/105A
鈥?/div>
Field-programmable (Ti-W fusible link)
鈥?/div>
16 input variables
鈥?/div>
8 output functions
鈥?/div>
64 transition terms
鈥?/div>
8-bit State Register
鈥?/div>
8-bit Output Register
鈥?/div>
2 transition Complement Arrays
鈥?/div>
Multiple clocks
鈥?/div>
Programmable Asynchronous Initialization
鈥?/div>
Power-on preset of all registers to 鈥?鈥?/div>
鈥?/div>
鈥淥n-chip鈥?diagnostic test mode features for
鈥?/div>
950mW power dissipation (typ.)
鈥?/div>
TTL compatible
鈥?/div>
J-K or S-R flip-flop functions
鈥?/div>
Automatic 鈥淗old鈥?states
鈥?/div>
3-State outputs
APPLICATIONS
access to state and output registers
or Output Enable
frequency (1/(t
IS1
+ t
CKO1
)
PIN CONFIGURATIONS
N Package
CLK 1
I7 2
I6 3
I5/CLK 4
I4 5
I3 6
I2 7
I1 8
I0 9
F7 10
F6 11
F5 12
F4 13
GND 14
28 V
CC
27 I8
26 I9
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 INIT/OE
18 F0
17 F1
16 F2
15 F3
N = Plastic DIP (600mil-wide)
A Package
I5/CLK I6
4
I4 5
I3 6
I2 7
I1 8
I0 9
F7 10
F6 11
12
13
14
15
16
17
18
3
I7 CLK V
CC
I8
1 28 27
2
I9
26
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 INIT/OE
鈥?/div>
Interface protocols
鈥?/div>
Sequence detectors
鈥?/div>
Peripheral controllers
鈥?/div>
Timing generators
鈥?/div>
Sequential circuits
鈥?/div>
Elevator contollers
鈥?/div>
Security locking systems
鈥?/div>
Counters
鈥?/div>
Shift registers
F5 F4 GND F3 F2 F1 F0
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic Dual In-Line (600mil-wide)
28-Pin Plastic Leaded Chip Carrier
OPERATING
FREQUENCY
55MHz (t
IS
+ t
CKO
)
55MHz (t
IS
+ t
CKO
)
ORDER CODE
PLUS405鈥?5N
PLUS405鈥?5A
DRAWING NUMBER
0413B
0401F
October 22, 1993
180
853鈥?546 11164
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