Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16
脳
45
脳
12)
PLS159A
DESCRIPTION
The PLS159A is a 3-State output, registered
logic element combining AND/OR gate arrays
with clocked J-K flip-flops. These J-K
flip-flops are dynamically convertible to
D-type via a 鈥渇old-back鈥?inverting buffer and
control gate F
C
. It features 8 registered I/O
outputs (F) in conjunction with 4 bidirectional
I/O lines (B). These yield variable I/O gate
and register configurations via control gates
(D, L) ranging from 16 inputs to 12 outputs.
The AND/OR arrays consist of 32 logic AND
gates, 13 control AND gates, and 21 OR
gates with fusible link connections for
programming I/O polarity and direction. All
AND gates are linked to 4 inputs (I),
bidirectional I/O lines (B), internal flip-flop
outputs (Q), and Complement Array output
(C). The Complement Array consists of a
NOR gate optionally linked to all AND gates
for generating and propagating
complementary AND terms.
On-chip T/C buffers couple either True (I, B,
Q) or Complement (I, B, Q, C) input polarities
to all AND gates, whose outputs can be
optionally linked to all OR gates. Any of the
32 AND gates can drive bidirectional I/O lines
(B), whose output polarity is individually
programmable through a set of Ex-OR gates
for implementing AND-OR or AND-NOR logic
functions. Similarly, any of the 32 AND gates
can drive the J-K inputs of all flip-flops. There
are 4 AND gates for the Asynchronous
Preset/Reset functions.
All flip-flops are positive edge-triggered and
can be used as input, output or I/O (for
interfacing with a bidirectional data bus) in
conjunction with load control gates (L),
steering inputs (I), (B), (Q) and
programmable output select lines (E).
The PLS159A is field-programmable,
enabling the user to quickly generate custom
patterns using standard programming
equipment.
FEATURES
鈥?/div>
High-speed version of PLS159
鈥?/div>
f
MAX
= 18MHz
鈥?/div>
25MHz clock rate
PIN CONFIGURATIONS
N Package
CLK
I0
I1
I2
I3
B0
B1
B2
B3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
F7
F6
F5
F4
F3
F2
F1
F0
OE
鈥?/div>
Field-Programmable (Ni-Cr link)
鈥?/div>
4 dedicated inputs
鈥?/div>
13 control gates
鈥?/div>
32 AND gates
鈥?/div>
21 OR gates
鈥?/div>
45 product terms:
鈥?/div>
32 logic terms
鈥?/div>
13 control terms
GND 10
鈥?/div>
4 bidirectional I/O lines
鈥?/div>
8 bidirectional registers
鈥?/div>
J-K, T, or D-type flip-flops
鈥?/div>
Power-on reset feature on all flip-flops
鈥?/div>
Asynchronous Preset/Reset
鈥?/div>
Complement Array
鈥?/div>
Active-High or -Low outputs
鈥?/div>
Programmable OE control
鈥?/div>
Positive edge-triggered clock
鈥?/div>
Input loading: 鈥?00
碌
A (max.)
鈥?/div>
Power dissipation: 750mW (typ.)
鈥?/div>
TTL compatible
鈥?/div>
3-State outputs
APPLICATIONS
(F
n
= 1)
N = Plastic Dual In-Line Package (300mil-wide)
A Package
I1
3
I2
I3
B0
B1
B2
4
5
6
7
8
9
10
11
12
13
I0 CLK V
CC
F7
2
1 20 19
18
17
16
15
14
F6
F5
F4
F3
F2
B3 GND OE F0 F1
A = Plastic Leaded Chip Carrier
鈥?/div>
Random sequential logic
鈥?/div>
Synchronous up/down counters
鈥?/div>
Shift registers
鈥?/div>
Bidirectional data buffers
鈥?/div>
Timing function generators
鈥?/div>
System controllers/synchronizers
鈥?/div>
Priority encoder/registers
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dual In-Line Package (300mil-wide)
20-Pin Plastic Leaded Chip Carrier
ORDER CODE
PLS159AN
PLS159AA
DRAWING NUMBER
0408D
0400E
October 22, 1993
25
853鈥?159 11164
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英文版
Analog IC
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Analog IC
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Programmable logic arrays 16 】 48 】 8
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英文版
Programmable logic arrays 16 】 48 】 8
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英文版
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